Ta-Ching Yeh
According to our database1,
Ta-Ching Yeh
authored at least 3 papers
between 2008 and 2019.
Collaborative distances:
Collaborative distances:
Timeline
2008
2010
2012
2014
2016
2018
0
1
2
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2019
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time.
IEEE J. Solid State Circuits, 2019
2018
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2008
Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008