T. Venkata Kalyan

Orcid: 0000-0001-6596-2292

According to our database1, T. Venkata Kalyan authored at least 13 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Cache Line Pinning for Mitigating Row Hammer Attack.
Proceedings of the 53rd International Conference on Parallel Processing, 2024

2023
A Graph Data Structure to Optimize Dynamic Graph Processing on GPUs.
CoRR, 2023

2022
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
A Scalable and Energy-Efficient Concurrent Binary Search Tree With Fatnodes.
IEEE Trans. Sustain. Comput., 2020

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2017
FatCBST: Concurrent Binary Search Tree with Fatnodes.
Proceedings of the 19th IEEE International Conference on High Performance Computing and Communications; 15th IEEE International Conference on Smart City; 3rd IEEE International Conference on Data Science and Systems, 2017

2014
EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices.
ACM Trans. Archit. Code Optim., 2014

SFFMap: Set-First Fill mapping for an energy efficient pipelined data cache.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Scattered refresh: An alternative refresh mechanism to reduce refresh cycle time.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Data remapping for an energy efficient burst chop in DRAM memory systems.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2012
Way Sharing Set Associative Cache Architecture.
Proceedings of the 25th International Conference on VLSI Design, 2012

2008
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Word-interleaved cache: an energy efficient data cache architecture.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008


  Loading...