T. S. Manivannan

According to our database, T. S. Manivannan authored at least 3 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

Optimization of DE-QG TFET using novel CIP and DCT techniques.

T. S. Manivannan, K. R. Pasupathy, Mohd Rizwan Uddin Shaikh, G. Lakshminarayanan

Microelectron. J., February, 2024

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile.

T. S. Manivannan, K. R. Pasupathy, G. Lakshminarayanan

Microelectron. J., 2024

2018

A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches.

T. S. Manivannan, Meena Srinivasan

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018