T. Raju Damarla

According to our database, T. Raju Damarla authored at least 7 papers between 1989 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

Faulty chip identification in a multi chip module system.

T. Raju Damarla, Moon J. Chung, Wei Su, Gerald T. Michael

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995

Multiple error detection and identification via signature analysis.

T. Raju Damarla, Charles E. Stroud, Avinash Sathaye

J. Electron. Test., 1995

Improving the efficiency of error identification via signature analysis.

Charles E. Stroud, T. Raju Damarla

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

A built-in self test scheme for VLSI.

T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1991

Spectral Techniques for Multiple-Valued Logic Circuits.

T. Raju Damarla, Fiaz Hossain

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

1990

Fault Detection in Multiple Valued Logic Circuits.

T. Raju Damarla

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1989

Fault Detection in Combinational Networks by Reed-Muller Transforms.

T. Raju Damarla, Mark G. Karpovsky

IEEE Trans. Computers, 1989