T. Nakano
According to our database1,
T. Nakano
authored at least 4 papers
between 1985 and 2023.
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Bibliography
2023
A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm<sup>2</sup> bit density with 3.2Gbps interface and 205MB/s program throughput.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2016
2006
J. Vis., 2006
1985
Test Pattern Considerations for Fault Tolerant High Density DRAM.
Proceedings of the Proceedings International Test Conference 1985, 1985