Szu-Yao Hung
According to our database1,
Szu-Yao Hung
authored at least 8 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation.
IEEE J. Solid State Circuits, October, 2024
2019
A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017
2015
A fast-settling high linearity auto gain control for broadband OFDM-based PLC system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013