Sylvain Guilley

Proceedings of the 3rd ACM SIGPLAN Program Protection and Reverse Engineering Workshop 2014, 2014

Hardware-enforced Protection against Software Reverse-Engineering based on an Instruction Set Encoding.

[BibT_eX]

[DOI]

Florian Praden

Proceedings of the 3rd ACM SIGPLAN Program Protection and Reverse Engineering Workshop 2014, 2014

Cryptographically secure shields.

[BibT_eX]

[DOI]

Jean-Michel Cioranesco

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

High-order timing attacks.

[BibT_eX]

[DOI]

Proceedings of the First Workshop on Cryptography and Security in Computing Systems, 2014

Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses.

[BibT_eX]

[DOI]

Proceedings of the 9th Workshop on Embedded Systems Security, 2014

DRECON: DPA Resistant Encryption by Construction.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014

HCODE: Hardware-Enhanced Real-Time CFI.

[BibT_eX]

[DOI]

Proceedings of the 4th Program Protection and Reverse Engineering Workshop, 2014

2013

A synthesis of side-channel attacks on elliptic curve cryptography in smart-cards.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2013

A formal study of two physical countermeasures against side channel attacks.

[BibT_eX]

[DOI]

Sébastien Briais

J. Cryptogr. Eng., 2013

From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2013

Formally Proved Security of Assembly Code Against Leakage.

[BibT_eX]

[DOI]

Pablo Rauzy

Zakaria Najm

IACR Cryptol. ePrint Arch., 2013

Formal Analysis of CRT-RSA Vigilant's Countermeasure Against the BellCoRe Attack.

[BibT_eX]

[DOI]

Pablo Rauzy

IACR Cryptol. ePrint Arch., 2013

Detecting Hidden Leakages.

[BibT_eX]

[DOI]

Amir Moradi

Annelie Heuser

IACR Cryptol. ePrint Arch., 2013

Dynamic Countermeasure Against the Zero Power Analysis.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

NICV: Normalized Inter-Class Variance for Detection of Side-Channel Leakage.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

Theory of masking with codewords in hardware: low-weight dth-order correlation-immune Boolean functions.

[BibT_eX]

[DOI]

Shivam Bhasin

Claude Carlet

IACR Cryptol. ePrint Arch., 2013

Multiply constant weight codes.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013

Side-channel indistinguishability.

[BibT_eX]

[DOI]

Claude Carlet

Proceedings of the HASP 2013, 2013

Software Camouflage.

[BibT_eX]

[DOI]

Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013

Fault Injection to Reverse Engineer DES-Like Cryptosystems.

[BibT_eX]

[DOI]

Proceedings of the Foundations and Practice of Security - 6th International Symposium, 2013

A low-entropy first-degree secure provable masking scheme for resource-constrained devices.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Embedded Systems Security, 2013

2012

Global Faults on Cryptographic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Fault Analysis in Cryptography, 2012

Portability of templates.

[BibT_eX]

[DOI]

M. Abdelaziz Elaabid

J. Cryptogr. Eng., 2012

Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

A First-Order Leak-Free Masking Countermeasure.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

Optimal First-Order Masking with Linear and Non-Linear Bijections.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

Leakage Squeezing of Order Two.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

3D Hardware Canaries.

[BibT_eX]

[DOI]

Sébastien Briais

Stéphane Caron

Jean-Michel Cioranesco

Jacques-Henri Jourdan

Arthur Milchior

David Naccache

Thibault Porteboeuf

IACR Cryptol. ePrint Arch., 2012

On the Optimality of Correlation Power Attack on Embedded Cryptographic Systems.

[BibT_eX]

[DOI]

Proceedings of the Information Security Theory and Practice. Security, Privacy and Trust in Computing Systems and Ambient Intelligent Ecosystems, 2012

Wavelet transform based pre-processing for side channel analysis.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications.

[BibT_eX]

[DOI]

Shivam Bhasin

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

System-Level Methods to Prevent Reverse-Engineering, Cloning, and Trojan Insertion.

[BibT_eX]

[DOI]

Proceedings of the Information Systems, Technology and Management, 2012

Comparison between Side-Channel Analysis Distinguishers.

[BibT_eX]

[DOI]

Proceedings of the Information and Communications Security - 14th International Conference, 2012

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Random Active Shield.

[BibT_eX]

[DOI]

Sébastien Briais

Jean-Michel Cioranesco

Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Towards Different Flavors of Combined Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

Same Values Power Analysis Using Special Points on Elliptic Curves.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

Low-Cost Countermeasure against RPA.

[BibT_eX]

[DOI]

Proceedings of the Smart Card Research and Advanced Applications, 2012

Protection des Accélérateurs Matériels de Cryptographie Symétrique. (Protection of Symmetric Cryptography Hardware Accelerators).

[BibT_eX]

[DOI]

, 2012

2011

Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks.

[BibT_eX]

[DOI]

IET Inf. Secur., 2011

Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks.

[BibT_eX]

[DOI]

Maxime Nassar

IACR Cryptol. ePrint Arch., 2011

Classification of High-Order Boolean Masking Schemes and Improvements of their Efficiency.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

Side-Channel Oscilloscope

[BibT_eX]

[DOI]

Sumanta Chaudhuri

CoRR, 2011

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback

[BibT_eX]

[DOI]

CoRR, 2011

FIRE: Fault Injection for Reverse Engineering.

[BibT_eX]

[DOI]

Manuel San Pedro

Mate Soos

Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011

Leakage Squeezing Countermeasure against High-Order Attacks.

[BibT_eX]

[DOI]

Houssem Maghrebi

Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011

Formal Framework for the Evaluation of Waveform Resynchronization Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011

"Re-synchronization by moments": An efficient solution to align Side-Channel traces.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Workshop on Information Forensics and Security, 2011

Efficient Dual-Rail Implementations in FPGA Using Block RAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

"Rank Correction": A New Side-Channel Approach for Secret Key Recovery.

[BibT_eX]

[DOI]

Proceedings of the Security Aspects in Information Technology, 2011

Formal security evaluation of hardware Boolean masking against second-order attacks.

[BibT_eX]

[DOI]

Houssem Maghrebi

Proceedings of the HOST 2011, 2011

Performance evaluation of protocols resilient to physical attacks.

[BibT_eX]

[DOI]

Proceedings of the HOST 2011, 2011

Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Embedded systems security: An evaluation methodology against Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2010

Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator.

[BibT_eX]

[DOI]

M. Abdelaziz Elaabid

IACR Cryptol. ePrint Arch., 2010

Combined Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the Information Security Applications - 11th International Workshop, 2010

Cross-Correlation Cartography.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Defeating Any Secret Cryptography with SCARE Attacks.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2010

First Principal Components Analysis: A New Side Channel Distinguisher.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - ICISC 2010, 2010

Improvement of power analysis attacks using Kalman filter.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2010

Entropy-based Power Attack.

[BibT_eX]

[DOI]

Proceedings of the HOST 2010, 2010

Fault Injection Resilience.

[BibT_eX]

[DOI]

Proceedings of the 2010 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2010

BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Far Correlation-based EMA with a precharacterized leakage model.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the Topics in Cryptology, 2010

Characterization of the Electromagnetic Side Channel in Frequency Domain.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - 6th International Conference, 2010

Countering early evaluation: an approach towards robust dual-rail precharge logic.

[BibT_eX]

[DOI]

Proceedings of the 5th Workshop on Embedded Systems Security, 2010

2009

Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.

[BibT_eX]

[DOI]

Laurent Sauvage

Yves Mathieu

ACM Trans. Reconfigurable Technol. Syst., 2009

High speed true random number generator based on open loop structures in FPGAs.

[BibT_eX]

[DOI]

Microelectron. J., 2009

DPL on Stratix II FPGA: What to Expect?.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2009

WDDL is Protected against Setup Time Violation Attacks.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Deconvolving Protected Signals.

[BibT_eX]

[DOI]

Proceedings of the The Forth International Conference on Availability, 2009

2008

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks

[BibT_eX]

[DOI]

CoRR, 2008

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008

Fault Analysis Attack on an FPGA AES Implementation.

[BibT_eX]

[DOI]

Proceedings of the NTMS 2008, 2008

Place-and-Route Impact on the Security of DPL Designs in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Efficient tiling patterns for reconfigurable gate arrays.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Silicon-level Solutions to Counteract Passive and Active Attacks.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

Practical Setup Time Violation Attacks on AES.

[BibT_eX]

[DOI]

Nidhal Selmane

Proceedings of the Seventh European Dependable Computing Conference, 2008

An 8x8 run-time reconfigurable FPGA embedded in a SoC.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Physical Design of FPGA Interconnect to Prevent Information Leakage.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

A fast pipelined multi-mode DES architecture operating in IP representation.

[BibT_eX]

[DOI]

Renaud Pacalet

Integr., 2007

Template Attacks with a Power Model.

[BibT_eX]

[DOI]

M. Abdelaziz Elaabid

IACR Cryptol. ePrint Arch., 2007

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Conference on Research, 2007

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.

[BibT_eX]

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

A Novel Asynchronous e-FPGA Architecture for Security Applications.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.

[BibT_eX]

[DOI]

Sumanta Chaudhuri

Proceedings of the FPL 2007, 2007

2006

FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

2005

The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations.

[BibT_eX]