Sylvain Girbal

Orcid: 0009-0008-7620-9069

According to our database1, Sylvain Girbal authored at least 25 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2023
Securing a RISC-V architecture: A dynamic approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2021


2020
Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

Open Source Hardware: An Opportunity For Critical Systems.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2020

2018
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems.
Des. Autom. Embed. Syst., 2018

Assessing Time Predictability Features of ARM Big. LITTLE Multicores.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017
Low-level implementation of the SISC protocol for thread-level speculation on a multi-core architecture.
Parallel Comput., 2017

2014
TERAFLUX: Harnessing dataflow in next generation teradevices.
Microprocess. Microsystems, 2014

Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems.
Proceedings of the 22nd International Conference on Real-Time Networks and Systems, 2014

2013

On the convergence of mainstream and mission-critical markets.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments.
ACM Trans. Archit. Code Optim., 2012

2010
ArchExplorer for Automatic Design Space Exploration.
IEEE Micro, 2010

CMA: Chip multi-accelerator.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

ArchExplorer.org: A methodology for facilitating a fair Comparison of research ideas.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

A memory interface for multi-purpose multi-stream accelerators.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Reconciling specialization and flexibility through compound circuits.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2007
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development.
IEEE Comput. Archit. Lett., 2007

2006
Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies.
Int. J. Parallel Program., 2006

Violated dependence analysis.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

2005
Facilitating the search for compositions of program transformations.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

2004
A Polyhedral Approach to Ease the Composition of Program Transformations.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

Putting Polyhedral Loop Transformations to Work.
Proceedings of the Languages and Compilers for Parallel Computing, 2003


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