Sylvain Clerc

According to our database, Sylvain Clerc authored at least 31 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Exploration of Low-Energy Floating-Point Flash Attention Mechanism for 18nm FD-SOI CMOS Integration at the Edge.

Joaquin Cornejo, Filipe Pouget, Sylvain Clerc, Tifenn Hirtzlin, Benoit Larras, Andreia Cathelin, Antoine Frappé

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

2023

Low-Power Event-Driven Spectrogram Extractor for Multiple Keyword Spotting: A proof of concept.

Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A 291nW Real-Time Event-Driven Spectrogram Extraction unit in 28nm FD-SOI CMOS for Keyword Spotting Application.

Soufiane Mourrane, Benoit Larras, Sylvain Clerc, Andreia Cathelin, Antoine Frappé

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2021

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies.

Sylvain Clerc, Kedar Janardan Dhori, Robin M. Wilson, Rohit Goel, Sébastien Marchal, Franck Pourchon, Christian Dutto, Ricardo Gomez Gomez

Proceedings of the 47th ESSCIRC 2021, 2021

2020

Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC).

Lucien J. Breems, Patrick Reynaert, Sylvain Clerc

IEEE J. Solid State Circuits, 2020

A 3.0μW@5fps QQVGA Self-Controlled Wake-Up Imager with On-Chip Motion Detection, Auto-Exposure and Object Recognition.

Arnaud Verdant, William Guicquero, Nicolas Royer, Guillaume Moritz, Sébastien Martin, Florent Lepin, Sylvain Choisnet, Fabrice Guellec, Benoît Deschamps, Sylvain Clerc, Jérôme Chossat

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI.

Ricardo Gomez Gomez, Edwige Bano, Andreia Cathelin, Sylvain Clerc

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

Comparative evaluation of Body Biasing and Voltage Scaling for Low-Power Design on 28nm UTBB FD-SOI Technology.

Ricardo Gomez Gomez, Edwige Bano, Sylvain Clerc

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications.

Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2017

A 0.40pJ/cycle 981 μm² voltage scalable digital frequency generator for SoC clocking.

Martin Cochet, Sylvain Clerc, Guenole Lallement, Fady Abouzeid, Philippe Roche, Jean-Luc Autran

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.

Martin Cochet, Sylvain Clerc, Mehdi Naceur, Pierre Schamberger, Damien Croain, Jean-Luc Autran, Philippe Roche

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

30% static power improvement on ARM Cortex^®-A53 using static biasing-anticipation.

Fady Abouzeid, Christophe Bernicot, Sylvain Clerc, Jean-Marc Daveau, Gilles Gasiot, Daniel Noblet, Dimitri Soussan, Philippe Roche

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.

Martin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.

Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart

IEEE J. Solid State Circuits, 2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.

Sylvain Clerc, Mehdi Saligane, Fady Abouzeid, Martin Cochet, Jean-Marc Daveau, Cyril Bottoni, David Bol, Julien De Vos, Dominique Zamora, Benjamin Coeffic, Dimitri Soussan, Damien Croain, Mehdi Naceur, Pierre Schamberger, Philippe Roche, Dennis Sylvester

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.

Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.

Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Gilles Gasiot, Fady Abouzeid, Sylvain Clerc, Lirida A. B. Naviner, Philippe Roche

Proceedings of the IEEE International Reliability Physics Symposium, 2015

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.

Fady Abouzeid, Sylvain Clerc, Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Damien Croain, Gilles Gasiot, Dimitri Soussan, Philippe Roche

Proceedings of the ESSCIRC Conference 2015, 2015

2014

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits.

Jean-Luc Autran, Maximilien Glorieux, Daniela Munteanu, Sylvain Clerc, Gilles Gasiot, Philippe Roche

Microelectron. Reliab., 2014

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.

Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Anis Feki, Sylvain Clerc, Lorenzo Ciampolini, Fabien Giner, Robin Wilson, Philippe Roche

IEEE J. Solid State Circuits, 2014

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.

Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.

Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Sylvain Clerc, Lorenzo Ciampolini, Philippe Roche

Proceedings of the ESSCIRC 2013, 2013

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs.

Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.

Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Dimitri Soussan, Philippe Roche

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance.

Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Philippe Roche

Proceedings of the 38th European Solid-State Circuit conference, 2012

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder.

Fady Abouzeid, Sylvain Clerc, Bertrand Pelloux-Prayer, Fabrice Argoud, Philippe Roche

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications.

Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard

ACM Trans. Design Autom. Electr. Syst., 2011

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform.

Sylvain Clerc, Fady Abouzeid, Fabrice Argoud, Abhay Kumar, Rajesh Kumar, Philippe Roche

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter.

Brice Lhomme, Yann Carminati, Bertrand Borot, Olivier Callen, Thierry Burdeau, Sylvain Clerc

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.

Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

A 45nm single power supply SRAM supporting low voltage operation down to 0.6V.

Sebastien Barasinski, Ludovic Camus, Sylvain Clerc

Proceedings of the ESSCIRC 2008, 2008