Sylvain Barraud

According to our database, Sylvain Barraud authored at least 24 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires.

Giovanni Almeida Matos, Jaime CalÇade Rodrigues, Michelly de Souza, Mikaël Cassé, Sylvain Barraud, Olivier Faynot, Marcelo Antonio Pavanello

Proceedings of the 21st International Conference on Electrical Engineering, 2024

Evaluation and implementation of High-Dimensionnal Computing for gesture recognition using sEMG signals.

Ancelin Salerno, Sylvain Barraud

Proceedings of the International Conference on Control, Automation and Diagnosis, 2024

2023

Integration of HfO2-based 3D OxRAM with GAA stacked-nanosheet transistor for high-density embedded memory.

T. Dubreuil, Sylvain Barraud, J.-M. Pedini, Jean-Michel Hartmann, F. Boulard, A. Sarrazin, A. Gharbi, Johannes Sturm, A. Lambert, S. Martin, Niccolo Castellani, A. Anotta, A. Magalhaes-Lucas, Aurelie Souhaite, François Andrieu

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

A novel 3D 1T1R RRAM architecture for memory-centric Hyperdimensional Computing.

T. Dubreuil, P. Amari, Sylvain Barraud, Joris Lacord, Eduardo Esmanhotto, Valentina Meli, S. Martin, Niccolo Castellani, Bernard Previtali, François Andrieu

Proceedings of the IEEE International Memory Workshop, 2022

2021

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors.

Michelly de Souza, Sylvain Barraud, Mikaël Cassé, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Wafer-scale fabrication of biologically sensitive Si nanowire FET: from pH sensing to electrical detection of DNA hybridization.

R. Midahuen, Bernard Previtali, C. Fontelaye, G. Nonglaton, V. Stambouli, Sylvain Barraud

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020

Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.

Mona Ezzadeen, D. Bosch, Bastien Giraud, Sylvain Barraud, Jean-Philippe Noël, Didier Lattard, Joris Lacord, Jean-Michel Portal, François Andrieu

CoRR, 2020

2019

Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors.

Renan Trevisoli, Rodrigo Trevisoli Doria, Sylvain Barraud, Marcelo Antonio Pavanello

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018

Performance & reliability of 3D architectures (πfet, Finfet, Ωfet).

Antoine Laurent, Xavier Garros, Sylvain Barraud, J. Pelloux-Prayer, Mikaël Cassé, Fred Gaillard, X. Federspiel, David Roy, E. Vincent, Gérard Ghibaudo

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Si MOS technology for spin-based quantum computing.

Louis Hutin, Benoit Bertrand, Romain Maurand, Alessandro Crippa, Matias Urdampilleta, Y. J. Kim, A. Amisse, H. Bohuslavskyi, L. Bourdet, Sylvain Barraud, Xavier Jehl, Yann-Michel Niquet, Marc Sanquer, C. Bauerle, Tristan Meunier, Silvano De Franceschi, Maud Vinet

Proceedings of the 48th European Solid-State Device Research Conference, 2018

Towards scalable silicon quantum computing.

Maud Vinet, Louis Hutin, Benoit Bertrand, Heorhii Bohuslavskyi, Andrea Corna, Anthony Amisse, Alessandro Crippa, Léo Bourdet, Romain Maurand, Sylvain Barraud, Matias Urdampilleta, Christopher Bäuerle, Marc Sanquer, Xavier Jehl, Yann-Michel Niquet, Silvano De Franceschi, Tristan Meunier

Proceedings of the 76th Device Research Conference, 2018

2017

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K.

Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello

Microelectron. Reliab., 2017

SOI CMOS technology for quantum information processing.

Louis Hutin, Benoit Bertrand, Romain Maurand, Matias Urdampilleta, Baptiste Jadot, H. Bohuslavskyi, L. Bourdet, Yann-Michel Niquet, Xavier Jehl, Sylvain Barraud, C. Bauerle, Tristan Meunier, Marc Sanquer, Silvano De Franceschi, Maud Vinet

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

A new method for junctionless transistors parameters extraction.

Renan Trevisoli Doria, Rodrigo Trevisoli Doria, Michelly de Souza, Marcelo Antonio Pavanello, Sylvain Barraud

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Drain current model for short-channel triple gate junctionless nanowire transistors.

Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello

Microelectron. Reliab., 2016

Analog performance of strained SOI nanowires down to 10K.

Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot

Proceedings of the 46th European Solid-State Device Research Conference, 2016

Statistical characterization of drain current local and global variability in sub 15nm Si/SiGe Trigate pMOSFETs.

R. Lavieville, Theano A. Karatsori, Christoforos G. Theodorou, Sylvain Barraud, C. A. Dimitriadis, Gérard Ghibaudo

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model.

J. Pelloux-Prayer, Mikaël Cassé, François Triozon, Sylvain Barraud, Yann-Michel Niquet, J.-L. Rouviere, Olivier Faynot, Gilles Reimbold

Proceedings of the 45th European Solid State Device Research Conference, 2015

Back-gate effects and detailed characterization of junctionless transistor.

Mukta Singh Parihar, Fanyu Liu, Carlos Navarro, Sylvain Barraud, Maryline Bawedin, Irina Ionica, Abhinav Kranti, Sorin Cristoloveanu

Proceedings of the 45th European Solid State Device Research Conference, 2015

2013

Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs.

Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Gérard Ghibaudo, Hiroshi Iwai, Gilles Reimbold

Proceedings of the European Solid-State Device Research Conference, 2013

Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations.

Remi Coquand, Sylvain Barraud, Mikaël Cassé, Masahiro Koyama, Virginie Maffini-Alvaro, Marie-Pierre Samson, Lucie Tosti, Xavier Mescot, Gérard Ghibaudo, Stéphane Monfray, Frédéric Boeuf, Olivier Faynot, Barbara De Salvo

Proceedings of the European Solid-State Device Research Conference, 2013

2012

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs.

Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities.

Veeresh Deshpande, Sylvain Barraud, Xavier Jehl, Romain Wacquez, Maud Vinet, Remi Coquand, B. Roche, B. Voisin, François Triozon, C. Vizioz, L. Tosti, Bernard Previtali, P. Perreau, T. Poiroux, Marc Sanquer, Olivier Faynot

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011

Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs.

Kiichi Tachi, Sylvain Barraud, Kuniyuki Kakushima, Hiroshi Iwai, Sorin Cristoloveanu, Thomas Ernst

Microelectron. Reliab., 2011