Sying-Jyan Wang

According to our database, Sying-Jyan Wang authored at least 87 papers between 1991 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips.

Katherine Shu-Min Li, Fang-Chi Wu, Jian-De Li, Sying-Jyan Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

2023

Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults.

Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Integr., March, 2023

Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing.

Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho

Proceedings of the IEEE International Test Conference, 2023

Implementing OIML R46 Communication Unit for DLMS/COSEM Security Suite 1 and Passing CTT V3.1 Test.

Chun-Tsai Chien, Chien-Lung Wang, I-En Liao, Sying-Jyan Wang

Proceedings of the IEEE International Conference on Networking, Sensing and Control, 2023

2022

Improving IJTAG Test Efficiency and Security.

Sying-Jyan Wang, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong

Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test.

Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang

Proceedings of the IEEE International Test Conference, 2022

Wafer Defect Pattern Classification with Explainable-Decision Tree Technique.

Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai

Proceedings of the IEEE International Test Conference, 2022

Trojan Insertions of Fully Programmable Valve Arrays.

Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho

Proceedings of the IEEE European Test Symposium, 2022

Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication.

Sying-Jyan Wang, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong

Proceedings of the IEEE 31st Asian Test Symposium, 2022

Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults.

Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning.

Sying-Jyan Wang, Yu-Sheng Chen, Katherine Shu-Min Li

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs.

Sying-Jyan Wang, Tzu-Heng Chang, Katherine Shu-Min Li

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques.

Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou

Proceedings of the IEEE International Test Conference, 2021

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.

Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu

Proceedings of the IEEE International Test Conference, 2021

Integrated Scratch Marker for Wafer Defect Diagnosis.

Katherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng

Proceedings of the IEEE International Test Conference in Asia, 2021

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering.

Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu

Proceedings of the 26th IEEE European Test Symposium, 2021

Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips.

Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Innovative Practice on Wafer Test Innovations.

Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning.

Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee

Proceedings of the IEEE International Test Conference, 2020

Watermarking for Paper-Based Digital Microfluidic Biochips.

Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Proceedings of the IEEE International Test Conference in Asia, 2020

Feature Selection for Malicious Traffic Detection with Machine Learning.

Sying-Jyan Wang, Cheng Xuan Cai, Yen-Wen Tseng, Katherine Shu-Min Li

Proceedings of the International Computer Symposium, 2020

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques.

Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, Gus Chang-Hung Han

Proceedings of the IEEE European Test Symposium, 2020

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.

Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips.

Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu

Microelectron. J., 2019

Exploiting distribution of unknown values in test responses to optimize test output compactors.

Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li

Integr., 2019

TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning.

Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee

Proceedings of the IEEE International Test Conference, 2019

Adversarial Attack against Modeling Attack on PUFs.

Sying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips.

Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang, Tsung-Yi Ho

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Register PUF with No Power-Up Restrictions.

Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Digital Rights Management for Paper-Based Microfluidic Biochips.

Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip.

Katherine Shu-Min Li, Sying-Jyan Wang

ACM Trans. Design Autom. Electr. Syst., 2017

Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis.

Katherine Shu-Min Li, Sying-Jyan Wang, Ruei-Ting Gu, Bo-Chuan Cheng

IEEE Des. Test, 2017

Design-for-testability for paper-based digital microfluidic biochips.

Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Testing Clock Distribution Networks.

Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Test and diagnosis of paper-based microfluidic biochips.

Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test generation for combinational hardware Trojans.

Sying-Jyan Wang, Jhih-Yu Wei, Shih-Heng Huang, Katherine Shu-Min Li

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Side-Channel Attack on Flipped Scan Chains.

Sying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips.

Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2014

Fast and accurate statistical static timing analysis.

Sying-Jyan Wang, Tsung-Huei Tzeng, Katherine Shu-Min Li

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Improving Output Compaction Efficiency with High Observability Scan Chains.

Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Optimized Pre-bond Test Methodology for Silicon Interposer Testing.

Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Delay Test with Embedded Test Pattern Generator.

Nan-Cheng Lai, Sying-Jyan Wang

J. Inf. Sci. Eng., 2013

Low-cost testing of TSVs in 3D stacks with pre-bond testable dies.

Sying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process.

Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Synthesis of 3D clock tree with pre-bond testability.

Sying-Jyan Wang, Cheng-Hao Lin, Katherine Shu-Min Li

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.

Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu

Proceedings of the 22nd Asian Test Symposium, 2013

Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator.

Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Power-Aware High-Level Synthesis With Clock Skew Management.

Tung-Hua Yeh, Sying-Jyan Wang

IEEE Trans. Very Large Scale Integr. Syst., 2012

Low-power delay test architecture for pre-bond test.

Sying-Jyan Wang, Han-Hsuan Hsu, Katherine Shu-Min Li

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

De Bruijn graph-based communication modeling for fault tolerance in smart grids.

Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2010

Thermal Safe High Level Test Synthesis for Hierarchical Testability.

Tung-Hua Yeh, Sying-Jyan Wang

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability.

Sying-Jyan Wang, Tung-Hua Yeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint.

Sying-Jyan Wang, Katherine Shu-Min Li, Shih-Cheng Chen, Huai-Yan Shiu, Yun-Lung Chu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Low Peak Power ATPG for n-Detection Test.

Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Level Converting Scan Flip-flops.

Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Layout-aware scan chain reorder for launch-off-shift transition test coverage.

Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li

ACM Trans. Design Autom. Electr. Syst., 2008

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction.

Po-Chang Tsai, Sying-Jyan Wang

IET Comput. Digit. Tech., 2008

Design and analysis of skewed-distribution scan chain partition for improved test data compression.

Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests.

Nan-Cheng Lai, Sying-Jyan Wang

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Test Data Compression for Minimum Test Application Time.

Po-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh

J. Inf. Sci. Eng., 2007

Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.

Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High-level test synthesis for delay fault testability.

Sying-Jyan Wang, Tung-Hua Yeh

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture.

Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li

Proceedings of the 16th Asian Test Symposium, 2007

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis.

Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li

Proceedings of the 16th Asian Test Symposium, 2007

Low-Capture-Power Test Generation by Specifying A Minimum Set of Controlling Inputs.

Nan-Cheng Lai, Sying-Jyan Wang

Proceedings of the 16th Asian Test Symposium, 2007

2006

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.

Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage.

Sying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li

Proceedings of the 15th Asian Test Symposium, 2006

2005

FSM-based programmable memory BIST with macro command.

Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Low power parallel multiplier with column bypassing.

Mingchen Wen, Sying-Jyan Wang, Yen-Nan Lin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Test Data Compression with Partial LFSR-Reseeding.

Yu-Hsuan Fu, Sying-Jyan Wang

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Low Power BIST with Smoother and Scan-Chain Reorder .

Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2002

Retiming-based logic synthesis for low-power.

Yu-Lung Hsu, Sying-Jyan Wang

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

A Reseeding Technique for LFSR-Based BIST Applications.

Nan-Cheng Li, Sying-Jyan Wang

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Distributed Diagnosis in Multistage Interconnection Networks.

Sying-Jyan Wang

J. Parallel Distributed Comput., 2001

Generating Efficient Tests for Continuous Scan.

Sying-Jyan Wang, Sheng-Nan Chiou

Proceedings of the 38th Design Automation Conference, 2001

2000

Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches.

Sying-Jyan Wang, Chia-Chun Lien

J. Inf. Sci. Eng., 2000

Efficient built-in self-test algorithm for memory.

Sying-Jyan Wang, Chen-Jung Wei

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1998

Testing and Diagnosis of Interconnect Structures in FPGAs.

Sying-Jyan Wang, Chao-Neng Huang

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Distributed Routing in a Fault-Tolerant Multistage Interconnection Network.

Sying-Jyan Wang

Inf. Process. Lett., 1997

Test and diagnosis of fault logic blocks in FPGAs.

Sying-Jyan Wang, Tsi-Ming Tsai

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Load-Balancing in Multistage Interconnection Networks under Multiple-Pass Routing.

Sying-Jyan Wang

J. Parallel Distributed Comput., 1996

Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.

Po-Ching Hsu, Sying-Jyan Wang

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1994

Algorithm-Based Fault Tolerance for FFT Networks.

Sying-Jyan Wang, Niraj K. Jha

IEEE Trans. Computers, 1994

Synthesis of Sequential Machines with Reduced Testing Cost.

Sying-Jyan Wang

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Design and synthesis of self-checking VLSI circuits.

Niraj K. Jha, Sying-Jyan Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992

Multiple Input Bridging Fault Detection in CMOS Sequential Circuits.

Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Design and Synthesis of Self-Checking VLSI Circuits and Systems.

Niraj K. Jha, Sying-Jyan Wang

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991