Syed Zahid Ahmed

According to our database1, Syed Zahid Ahmed authored at least 18 papers between 2008 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2019
High-throughput parallel DWT hardware architecture implemented on an FPGA-based platform.
J. Real Time Image Process., 2019

2016
Logarithmic Discrete Wavelet Transform for Medical Image Compression with Diagnostic Quality.
EAI Endorsed Trans. Pervasive Health Technol., 2016

A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

High frame rate medical quality video compression for tele-EEG.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Medical images compression with clinical diagnostic quality using logarithmic DWT.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree.
ACM Trans. Reconfigurable Technol. Syst., 2015

Synchronizing physiological data and video in a telemedicine application: A multimedia approach.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

2014
A power-efficient adaptive heapsort for fpga-based image coding application (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Fast and Power Efficient Heapsort IP for Image Compression Application.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative Coding.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Design and analysis of an FPGA based encoder SoC for locally stationary image source.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2010
Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Dynamic Reconfigurable MRAM based FPGA.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008


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