Syed Waqar Nabi

Orcid: 0000-0003-3835-4851

According to our database1, Syed Waqar Nabi authored at least 35 papers between 2008 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Integrating Socially Responsible Computing Competencies in Computer Science and Software Engineering Education.
Proceedings of the 9th Conference on Computing Education Practice, 2025

2024
The Development of Students' Professional Competencies on a Work-Based Software Engineering Program.
Proceedings of the 55th ACM Technical Symposium on Computer Science Education, 2024

2023
On Students' Experiences with Algorithm Tracing using Pair Programming.
Proceedings of the 2023 ACM Conference on International Computing Education Research, 2023

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis.
Proceedings of the International Conference on Field Programmable Technology, 2023

Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Dynamically Scheduled Memory Operations in Static High-Level Synthesis.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

The Development of Students' Employability Skills on a Work-Based Software Engineering Degree Programme.
Proceedings of the IEEE Frontiers in Education Conference, 2022

2021
PERCEPTRON: an open-source GPU-accelerated proteoform identification pipeline for top-down proteomics.
Nucleic Acids Res., 2021

English versus Native Language for Higher Education in Computer Science: A Pilot Study.
Proceedings of the Koli Calling '21: 21st Koli Calling International Conference on Computing Education Research, Joensuu, Finland, November 18, 2021

Professional Competencies in Computing Education: Pedagogies and Assessment.
Proceedings of the 2021 Working Group Reports on Innovation and Technology in Computer Science Education, 2021

Toward Practical Computing Competencies.
Proceedings of the ITiCSE '21: Proceedings of the 26th ACM Conference on Innovation and Technology in Computer Science Education V.2, Virtual Event, Germany, June 26, 2021

2020
Deep Learnability: Using Neural Networks to Quantify Language Similarity and Learnability.
Frontiers Artif. Intell., 2020

Keeping Software Engineering Students in Touch with Not Only What They are to Learn, But with Why.
Proceedings of the 32nd IEEE Conference on Software Engineering Education and Training, 2020

Online Delivery of Intensive Software Engineering Education during the COVID-19 Pandemic.
Proceedings of the 32nd IEEE Conference on Software Engineering Education and Training, 2020

2019
FPGA design space exploration for scientific HPC applications using a fast and accurate cost model based on roofline analysis.
J. Parallel Distributed Comput., 2019

Automatic Pipelining and Vectorization of Scientific Code for FPGAs.
Int. J. Reconfigurable Comput., 2019

Type-Driven Automated Program Transformations and Cost Modelling for Optimising Streaming Programs on FPGAs.
Int. J. Parallel Program., 2019

Towards Automatic Transformation of Legacy Scientific Code into OpenCL for Optimal Performance on FPGAs.
CoRR, 2019

Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program Transformations.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
MP-STREAM: A Memory Performance Benchmark for Design Space Exploration on Heterogeneous HPC Devices.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2016
A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

2015
An Intermediate Language and Estimator for Automated Design Space Exploration on FPGAs.
CoRR, 2015

A Reconfigurable Vector Instruction Processor for Accelerating a Convection Parametrization Model on FPGAs.
CoRR, 2015

Using type transformations to generate program variants for FPGA design space exploration.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

FPGAs as Components in Heterogeneous High-Performance Computing Systems: Raising the Abstraction Level.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

FPGA Port of a Large Scientific Model from Legacy Code: The Emanuel Convection Scheme.
Proceedings of the Parallel Computing: On the Road to Exascale, 2015

2012
Optimal Adjustment Parameters for EPC Global RFID Anti-collision Q-Algorithm in Different Traffic Scenarios.
Proceedings of the 10th International Conference on Frontiers of Information Technology, 2012

2010
Data Confidentiality and Integrity Issues and Role of Information Security Management Standard, Policies and Practices - An Empirical Study of Telecommunication Industry in Pakistan.
Proceedings of the Security Technology, Disaster Recovery and Business Continuity, 2010

A high-level language for programming a NoC-based Dynamic Reconfiguration Infrastructure.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009
A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices.
PhD thesis, 2009

2008
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor.
Proceedings of the FPL 2008, 2008

A Dynamically Reconfigurable Hardware Co-Processor for a Multi-Standard Wireless MAC Processor.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008


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