Syed Suhaib

IEEE Trans. Very Large Scale Integr. Syst., 2008

Formal Transformation of a KPN Specification to a GALS Implementation.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2008

2007

Formal Methods for Intellectual Property Composition Across Synchronization Domains.

[BibT_eX]

[DOI]

PhD thesis, 2007

Dataflow Architectures for GALS.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, 2007

2006

Validating Families of Latency Insensitive Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

A Trace Based Framework for Validation of SoC Designs with GALS Systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Polychronous Methodology For System Design: A True Concurrency Approach.

[BibT_eX]

[DOI]

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

XFM: An incremental methodology for developing formal models.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

A Functional Programming Framework for Latency Insensitive Protocol Validation.

[BibT_eX]

[DOI]

Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

System Level Design Methodology for System On Chips using Multi-Threaded Graphs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2004

A Formally Verified Application-Level Framework for Real-Time Scheduling on POSIX Real-Time Operating Systems.

[BibT_eX]

[DOI]

IEEE Trans. Software Eng., 2004

Extreme Formal Modeling (XFM) for Hardware Models.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Effects of property ordering in an incremental formal modeling methodology.

[BibT_eX]

[DOI]