Syed M. A. H. Jafri
According to our database1,
Syed M. A. H. Jafri
authored at least 37 papers
between 2010 and 2023.
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Bibliography
2023
Microprocess. Microsystems, 2023
2021
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators.
ACM Trans. Archit. Code Optim., 2021
2019
eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.
CoRR, 2019
2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017
SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs.
IEEE Trans. Computers, 2016
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
2015
TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs.
Microprocess. Microsystems, 2015
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs.
ACM J. Emerg. Technol. Comput. Syst., 2015
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs.
Proceedings of the 28th International Conference on VLSI Design, 2015
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
2014
Design of the coarse-grained reconfigurable architecture DART with on-line error detection.
Microprocess. Microsystems, 2014
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric.
Microprocess. Microsystems, 2014
Des. Autom. Embed. Syst., 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes.
Microprocess. Microsystems, 2013
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Hierarchical Supporting Structure for Dynamic Organization in Many-core Computing Systems.
Proceedings of the PECCS 2013, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.
Proceedings of the PECCS 2012, 2012
2011
Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010