Syed Ershad Ahmed

Orcid: 0000-0003-0333-9387

According to our database1, Syed Ershad Ahmed authored at least 36 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders.
Circuits Syst. Signal Process., July, 2024

ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks.
IEEE Access, 2024

Energy-Efficient Ternary Multiplier.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications.
IEEE Embed. Syst. Lett., September, 2023

Design methodology for highly accurate approximate multipliers for error resilient applications.
Comput. Electr. Eng., September, 2023

A General Methodology to Optimize Flagged Constant Addition.
J. Circuits Syst. Comput., January, 2023

Improved approximate multiplier architecture for image processing and neural network applications.
Microprocess. Microsystems, 2023

Power Efficient Approximate Ternary Subtractor for Image Processing Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

Low-Power Approximate Multiplier Architecture for Error Resilient Applications.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2023

Low Power Approximate Divider and Square Root Circuits for Error Resilient Applications.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2023

Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications.
Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2023

Design of Energy Efficient Posit Multiplier.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022
Design and exploration of low-power SAD architectures using approximate compressors for Integer Motion Estimation.
Microprocess. Microsystems, October, 2022

A High-Speed and Power-Efficient Approximate Adder for Image Processing Applications.
J. Circuits Syst. Comput., 2022

Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module.
IEEE Embed. Syst. Lett., 2022

Compressor based hybrid approximate multiplier architectures with efficient error correction logic.
Comput. Electr. Eng., 2022

2021
An Efficient Hardware Approach for Approximate Logarithmic Computation.
J. Circuits Syst. Comput., 2021

DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications.
IEEE Embed. Syst. Lett., 2021

Lower part OR based Approximate Multiplier for Error Resilient Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Approximate Multiplier Architectures for Error Resilient Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Power-Efficient MLOA for error resilient applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing.
Proceedings of the Machine Learning, Image Processing, Network Security and Data Sciences, 2020

2019
An Improved Logarithmic Multiplier for Media Processing.
J. Signal Process. Syst., 2019

2018
Improved designs of digit-by-digit decimal multiplier.
Integr., 2018

2016
A Hybrid Energy Efficient Digital Comparator.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An Iterative Logarithmic Multiplier with Improved Precision.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2014
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2012
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Modified Twin Precision Multiplier with 2D Bypassing Technique.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
A Prefix Based Reconfigurable Adder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011


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