Sybille Hellebrand

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

ATPG-based grading of strong fault-secureness.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Are Robust Circuits Really Robust?

[BibT_eX]

[DOI]

Marc Hunger

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Signature Rollback - A Technique for Testing Robust Circuits.

[BibT_eX]

[DOI]

Uranmandakh Amgalan

Christian Hachmann

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Modular Memory BIST for Optimized Memory Repair.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Verification and Analysis of Self-Checking Properties through ATPG.

[BibT_eX]

[DOI]

Marc Hunger

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007

An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip.

[BibT_eX]

[DOI]

Int. J. High Perform. Syst. Archit., 2007

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.

[BibT_eX]

[DOI]

Philipp Öhler

Proceedings of the 12th European Test Symposium, 2007

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.

[BibT_eX]

[DOI]

Christian G. Zoellin

Stefan Ludwig

Torsten Coym

Bernd Straube

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.

[BibT_eX]

[DOI]

Philipp Öhler

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).

[BibT_eX]

[DOI]

it Inf. Technol., 2006

2005

Low power embedded DRAMs with high quality error correcting capabilities.

[BibT_eX]

[DOI]

Philipp Öhler

Proceedings of the 10th European Test Symposium, 2005

2004

Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.

[BibT_eX]

[DOI]

Armin Würtenberger

Christofer S. Tautermann

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

A Hybrid Coding Strategy For Optimized Test Data Compression.

[BibT_eX]

[DOI]

Armin Würtenberger

Christofer S. Tautermann

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Efficient Online and Offline Testing of Embedded DRAMs.

[BibT_eX]

[DOI]

Alexander A. Ivaniuk

Yuri V. Klimets

IEEE Trans. Computers, 2002

A Mixed-Mode BIST Scheme Based on Folding Compression.

[BibT_eX]

[DOI]

Huaguo Liang

J. Comput. Sci. Technol., 2002

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.

[BibT_eX]

[DOI]

Huaguo Liang

J. Electron. Test., 2002

2001

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.

[BibT_eX]

[DOI]

Huaguo Liang

J. Electron. Test., 2001

1999

Error Detecting Refreshment for Embedded DRAMs.

[BibT_eX]

[DOI]

Alexander A. Ivaniuk

Yuri V. Klimets

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.

[BibT_eX]

[DOI]

I. V. Bykov

Proceedings of the Dependable Computing, 1999

Symmetric Transparent BIST for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

Mixed-Mode BIST Using Embedded Processors.

[BibT_eX]

[DOI]

Andre Hertwig

J. Electron. Test., 1998

Synthesizing Fast, Online-Testable Control Units.

[BibT_eX]

[DOI]

Andre Hertwig

IEEE Des. Test Comput., 1998

Fast Self-Recovering Controllers.

[BibT_eX]

[DOI]

Andre Hertwig

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

STARBIST: Scan Autocorrelated Random Pattern Generation.

[BibT_eX]

[DOI]

Kun-Han Tsai

Malgorzata Marek-Sadowska

Janusz Rajski

Proceedings of the 34st Conference on Design Automation, 1997

1995

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

Janusz Rajski

Steffen Tarnick

Srikanth Venkataraman

Bernard Courtois

IEEE Trans. Computers, 1995

Pattern generation for a deterministic BIST scheme.

[BibT_eX]

[DOI]

Birgit Reeb

Steffen Tarnick

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

An efficient procedure for the synthesis of fast self-testable controller structures.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of Self-Testable Controllers.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992

The pseudoexhaustive test of sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.

[BibT_eX]

[DOI]