Swaroop Ghosh

CoRR, 2024

AI-driven Reverse Engineering of QML Models.

[BibT_eX]

[DOI]

Archisman Ghosh

CoRR, 2024

Security Concerns in Quantum Machine Learning as a Service.

[BibT_eX]

[DOI]

CoRR, 2024

The Quantum Imitation Game: Reverse Engineering of Quantum Machine Learning Models.

[BibT_eX]

[DOI]

Archisman Ghosh

CoRR, 2024

STIQ: Safeguarding Training and Inferencing of Quantum Neural Networks from Untrusted Cloud.

[BibT_eX]

[DOI]

CoRR, 2024

Investigating impact of bit-flip errors in control electronics on quantum computation.

[BibT_eX]

[DOI]

CoRR, 2024

Guardians of the Quantum GAN.

[BibT_eX]

[DOI]

CoRR, 2024

Magic Mirror on the Wall, How to Benchmark Quantum Error Correction Codes, Overall ?

[BibT_eX]

[DOI]

CoRR, 2024

MITS: A Quantum Sorcerer Stone For Designing Surface Codes.

[BibT_eX]

[DOI]

CoRR, 2024

Designing Hash and Encryption Engines using Quantum Computing.

[BibT_eX]

[DOI]

Rupshali Roy

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Stealthy SWAPs: Adversarial SWAP Injection in Multi-Tenant Quantum Computing.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Trojan Taxonomy in Quantum Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Obfuscating Quantum Hybrid-Classical Algorithms for Security and Privacy.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Hardware Trojans in Quantum Circuits, Their Impacts, and Defense.

[BibT_eX]

[DOI]

Rupshali Roy

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Non-parametric Greedy Optimization of Parametric Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Trojan Attacks on Variational Quantum Circuits and Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

SoK Paper: Security Concerns in Quantum Machine Learning as a Service.

[BibT_eX]

[DOI]

Proceedings of the 13th International Workshop on Hardware and Architectural Support for Security and Privacy, 2024

Evaluating Efficacy of Model Stealing Attacks and Defenses on Quantum Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Application of Quantum Tensor Networks for Protein Classification.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Q-Embroidery: A Study on Weaving Quantum Error Correction into the Fabric of Quantum Classifiers.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

AltGraph: Redesigning Quantum Circuits Using Generative Graph Models for Efficient Optimization.

[BibT_eX]

[DOI]

Collin Beaudoin

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023

Quantum Random Access Memory for Dummies.

[BibT_eX]

[DOI]

Sensors, September, 2023

Large-Scale Quantum Approximate Optimization via Divide-and-Conquer.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

SCANN: Side Channel Analysis of Spiking Neural Networks.

[BibT_eX]

[DOI]

Cryptogr., June, 2023

WEPRO: Weight Prediction for Efficient Optimization of Hybrid Quantum-Classical Algorithms.

[BibT_eX]

[DOI]

CoRR, 2023

TrojanNet: Detecting Trojans in Quantum Circuits using Machine Learning.

[BibT_eX]

[DOI]

CoRR, 2023

A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays.

[BibT_eX]

[DOI]

CoRR, 2023

Random Relabeling for Efficient Machine Unlearning.

[BibT_eX]

[DOI]

CoRR, 2023

Predicting Side Effect of Drug Molecules using Recurrent Neural Networks.

[BibT_eX]

[DOI]

Collin Beaudoin

CoRR, 2023

Randomized Reversible Gate-Based Obfuscation for Secured Compilation of Quantum Circuit.

[BibT_eX]

[DOI]

CoRR, 2023

Trainable PQC-Based QRAM for Quantum Storage.

[BibT_eX]

[DOI]

IEEE Access, 2023

Shot Optimization in Quantum Machine Learning Architectures to Accelerate Training.

[BibT_eX]

[DOI]

IEEE Access, 2023

Quantum Error Correction For Dummies.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Knowledge Distillation in Quantum Neural Network Using Approximate Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Addressing Resiliency of In-Memory Floating Point Computation.

[BibT_eX]

[DOI]

Derek Weast

IEEE Trans. Very Large Scale Integr. Syst., 2022

Energy-based Generative Models for Target-specific Drug Discovery.

[BibT_eX]

[DOI]

Collin Beaudoin

CoRR, 2022

Approximate Quantum Random Access Memory Architectures.

[BibT_eX]

[DOI]

CoRR, 2022

Quantum Machine Learning for Material Synthesis and Hardware Security.

[BibT_eX]

[DOI]

CoRR, 2022

DeepQMLP: A Scalable Quantum-Classical Hybrid DeepNeural Network Architecture for Classification.

[BibT_eX]

[DOI]

CoRR, 2022

Shuttle-Exploiting Attacks and Their Defenses in Trapped-Ion Quantum Computers.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

IEEE Access, 2022

Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

HeapSafe: Securing Unprotected Heaps in RISC-V.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Optimization of Quantum Read-Only Memory Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Robust and Secure Hybrid Quantum-Classical Computation on Untrusted Cloud-Based Quantum Hardware.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Hardware and Architectural Support for Security and Privacy, 2022

A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Security Aspects of Quantum Machine Learning: Opportunities, Threats and Defenses.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Session details: Session 5B: VLSI Design + VLSI Circuits and Power Aware Design 2.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural Networks.

[BibT_eX]

[DOI]

Sachhidh Kannan

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Scalable Variational Quantum Circuits for Autoencoder-based Drug Discovery.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM.

[BibT_eX]

[DOI]

Farid Uddin Ahmed

Masud H. Chowdhury

IEEE Trans. Very Large Scale Integr. Syst., 2021

SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Reconfigurable and Dense Analog Circuit Design Using Two Terminal Resistive Memory.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Quantum PUF for Security and Trust in Quantum Computing.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories.

[BibT_eX]

[DOI]

CoRR, 2021

A Quantum Circuit Obfuscation Methodology for Security and Privacy.

[BibT_eX]

[DOI]

CoRR, 2021

Drug Discovery Approaches using Quantum Machine Learning.

[BibT_eX]

[DOI]

CoRR, 2021

Quantum Generative Models for Small Molecule Drug Discovery.

[BibT_eX]

[DOI]

Rasit Onur Topaloglu

CoRR, 2021

Short Paper: A Quantum Circuit Obfuscation Methodology for Security and Privacy.

[BibT_eX]

[DOI]

Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021

Impact of Noise on the Resilience and the Security of Quantum Computing.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Split Compilation for Security of Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Survey and Tutorial on Security and Resilience of Quantum Computing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Invited: Drug Discovery Approaches using Quantum Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Cache-Out: Leaking Cache Memory Using Hardware Trojan.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

HarTBleed: Using Hardware Trojans for Data Leakage Exploits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Test Methodologies and Test-Time Compression for Emerging Non-Volatile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2020

Design, Analysis and Application of Embedded Resistive RAM Based Strong Arbiter PUF.

[BibT_eX]

[DOI]

Srinivas Katkoori

IEEE Trans. Dependable Secur. Comput., 2020

Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering.

[BibT_eX]

[DOI]

Deepak Vontela

Ithihasa Reddy Nirmala

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TrappeD: DRAM Trojan Designs for Information Leakage and Fault Injection Attacks.

[BibT_eX]

[DOI]

CoRR, 2020

Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers.

[BibT_eX]

[DOI]

IEEE Access, 2020

Recent Advances in Emerging Technology-based Security Primitives, Attacks and Mitigation.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Assuring Security and Reliability of Emerging Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Multi-Bit Read and Write Methodologies for Diode-MTJ Crossbar Array.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Improving Reliability of Quantum True Random Number Generator using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Resiliency analysis and improvement of variational quantum factoring in superconducting qubit.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Analysis of crosstalk in NISQ devices and security implications in multi-programming regime.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

FAuto: An Efficient GMM-HMM FPGA Implementation for Behavior Estimation in Autonomous Systems.

[BibT_eX]

[DOI]

Navyata Gattu

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Power Side Channel Attack Analysis and Detection.

[BibT_eX]

[DOI]

Navyata Gattu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Noise Resilient Compilation Policies for Quantum Approximate Optimization Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Quantum-Soft QUBO Suppression for Accurate Object Detection.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020, 2020

Accelerating Quantum Approximate Optimization Algorithm using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Design-Space Exploration of Quantum Approximate Optimization Algorithm under Noise.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.

[BibT_eX]

[DOI]

Srivatsa Rangachar Srinivasa

IEEE Trans. Emerg. Top. Comput., 2019

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.

[BibT_eX]

[DOI]

Akshay Krishna Ramanathan

Vijaykrishnan Narayanan

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Family of Compact Non-Volatile Flip-Flops With Ferroelectric FET.

[BibT_eX]

[DOI]

Sung-Hao Lin

Sandeep Krishna Thirumala

Sumeet Kumar Gupta

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

TCAD EIC Message: February 2019.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Perspective on Test Methodologies for Supervised Machine Learning Accelerators.

[BibT_eX]

[DOI]

Jongsun Park

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Analysis of Quantum Approximate Optimization Algorithm under Realistic Noise in Superconducting Qubits.

[BibT_eX]

[DOI]

CoRR, 2019

RF-Trojan: Leaking Kernel Data Using Register File Trojan.

[BibT_eX]

[DOI]

CoRR, 2019

Study of Decoherence in Quantum Computers: A Circuit-Design Perspective.

[BibT_eX]

[DOI]

CoRR, 2019

Logic Obfuscation using Metasurface Holography.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

iMACE: In-Memory Acceleration of Classic McEliece Encoder.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing.

[BibT_eX]

[DOI]

Anupam Chattopadhyay

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Meeting the Conflicting Goals of Low-Power and Resiliency Using Emerging Memories : (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

FPCAS: In-Memory Floating Point Computations for Autonomous Systems.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2019

MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper.

[BibT_eX]

[DOI]

Debjyoti Bhattacharjee

Proceedings of the International Conference on Computer-Aided Design, 2019

ENTT: A Family of Emerging NVM-based Trojan Triggers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

TOIC: Timing Obfuscated Integrated Circuits.

[BibT_eX]

[DOI]

Sujay S. Hosur

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

True Random Number Generator using Superconducting Qubits.

[BibT_eX]

[DOI]

Proceedings of the Device Research Conference, 2019

Hardware Trojans in Emerging Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FIXER: Flow Integrity Extensions for Embedded RISC-V.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

QURE: Qubit Re-allocation in Noisy Intermediate-Scale Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

CSRO-Based Reconfigurable True Random Number Generator Using RRAM.

[BibT_eX]

[DOI]

Srinivas Katkoori

IEEE Trans. Very Large Scale Integr. Syst., 2018

VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting.

[BibT_eX]

[DOI]

Jaydeep P. Kulkarni

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.

[BibT_eX]

[DOI]

Jaydeep Kulkarni

ACM J. Emerg. Technol. Comput. Syst., 2018

Test challenges and solutions for emerging non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Test of Supply Noise for Emerging Non-Volatile Memory.

[BibT_eX]

[DOI]

Srivatsa Rangachar Srinivasa

Proceedings of the IEEE International Test Conference, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.

[BibT_eX]

[DOI]

Akshay Krishna Ramanathan

Meng-Fan Marvin Chang

Jack Sampson

Vijaykrishnan Narayanan

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Information Leakage Attacks on Emerging Non-Volatile Memory and Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.

[BibT_eX]

[DOI]

Deepak Vontela

Ithihasa Reddy Nirmala

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Fault injection attacks on emerging non-volatile memory and countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Analysis of Row Hammer Attack on STTRAM.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

How Multi-Threshold Designs Can Protect Analog IPs.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

CTCG: Charge-trap based camouflaged gates for reverse engineering prevention.

[BibT_eX]

[DOI]

Sandeep Krishna Thirumala

Sung-Hao Lin

Sumeet Kumar Gupta

Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Novel application of spintronics in computing, sensing, storage and cybersecurity.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions.

[BibT_eX]

[DOI]

Jongsun Park

J. Hardw. Syst. Secur., 2017

Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2017

A Novel Interconnect Camouflaging Technique using Transistor Threshold Voltage.

[BibT_eX]

[DOI]

CoRR, 2017

Methodologies to exploit ATPG tools for de-camouflaging.

[BibT_eX]

[DOI]

Deepakreddy Vontela

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory.

[BibT_eX]

[DOI]

Alexander Holst

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Side-Channel Attack on STTRAM Based Cache for Cryptographic Application.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Threshold voltage defined multi-input complex gates.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Novel magnetic burn-in for retention testing of STTRAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Droop mitigating last level cache architecture for STTRAM.

[BibT_eX]

[DOI]

Radha Krishna Aluru

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Session 13 - Security circuits and systems.

[BibT_eX]

[DOI]

Xin Li

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions.

[BibT_eX]

[DOI]

Proc. IEEE, 2016

Robust Self-Collapsing Level-Shifter for Wide Voltage Operation.

[BibT_eX]

[DOI]

J. Low Power Electron., 2016

Spintronic PUFs for Security, Trust, and Authentication.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Overview of Circuits, Systems, and Applications of Spintronics.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Retention Testing Methodology for STTRAM.

[BibT_eX]

[DOI]

Srikant Srinivasan

IEEE Des. Test, 2016

Side Channel Attacks on STTRAM and Low-Overhead Countermeasures.

[BibT_eX]

[DOI]

Helia Naeimi

CoRR, 2016

Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.

[BibT_eX]

[DOI]

CoRR, 2016

Multi-Bit Read and Write Methodologies for Diode-STTRAM Crossbar Array.

[BibT_eX]

[DOI]

Radha Krishna Aluru

Rashmi Jha

CoRR, 2016

Attack resilient architecture to replace embedded Flash with STTRAM in homogeneous IoTs.

[BibT_eX]

[DOI]

CoRR, 2016

A strong arbiter PUF using resistive RAM.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency.

[BibT_eX]

[DOI]

Jinil Chung

Jongsun Park

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A strong arbiter PUF using resistive RAM within 1T-1R memory architecture.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Security and privacy threats to on-chip non-volatile memories and countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A novel threshold voltage defined switch for circuit camouflaging.

[BibT_eX]

[DOI]

Ithihasa Reddy Nirmala

Deepak Vontela

Proceedings of the 21th IEEE European Test Symposium, 2016

Side channel attacks on STTRAM and low-overhead countermeasures.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Data privacy in non-volatile cache: Challenges, attack models and solutions.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

Domain Wall Magnets for Embedded Memory and Hardware Security.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

How Secure Are Printed Circuit Boards Against Trojan Attacks?

[BibT_eX]

[DOI]

Abhishek Basak

IEEE Des. Test, 2015

Schmitt-Trigger-based Recycling Sensor and Robust and High-Quality PUFs for Counterfeit IC Detection.

[BibT_eX]

[DOI]

Cheng-Wei Lin

CoRR, 2015

Threshold Voltage-Defined Switches for Programmable Gates.

[BibT_eX]

[DOI]

CoRR, 2015

Spintronics for associative computation and hardware security.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Novel self-calibrating recycling sensor using Schmitt-Trigger and voltage boosting for fine-grained detection.

[BibT_eX]

[DOI]

Cheng-Wei Lin

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design and analysis of novel SRAM PUFs with embedded latch for robustness.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A novel slope detection technique for robust STTRAM sensing.

[BibT_eX]

[DOI]

Jaydeep P. Kulkarni

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Design and analysis of 6-T 2-MTJ ternary Content Addressable Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality.

[BibT_eX]

[DOI]

Cheng-Wei Lin

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Impact of process-variations in STTRAM and adaptive boosting for robustness.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Self-correcting STTRAM under magnetic field attacks.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Domain wall memory based digital signal processors for area and energy-efficiency.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Modeling of Retention Time for High-Speed Embedded Dynamic Random Access Memories.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Energy Barrier Model of SRAM for Improved Energy and Error Rates.

[BibT_eX]

[DOI]

Jayita Das

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Synergistic circuit and system design for energy-efficient and robust domain wall caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

DWM-PUF: A low-overhead, memory-based security primitive.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Design methodologies for high density domain wall memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy centric model of SRAM write operation for improved energy and error rates.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011

Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Effect of Variations and Variation Tolerance in Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010

Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.

[BibT_eX]

[DOI]

Debabrata Mohapatra

Georgios Karakonstantis

IEEE Trans. Very Large Scale Integr. Syst., 2010

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era.

[BibT_eX]

[DOI]

Proc. IEEE, 2010

2009

Coping with Variations through System-Level Design.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2008

O<sup>2</sup>C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.

[BibT_eX]

[DOI]

Patrick Ndai

Proceedings of the Design, Automation and Test in Europe, 2008

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Low-Power and testable circuit synthesis using Shannon decomposition.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs.

[BibT_eX]

[DOI]

Jing Li

Proceedings of the 2007 IEEE International Test Conference, 2007

Tolerance to Small Delay Defects by Adaptive Clock Stretching.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

A built-in self-testing method for embedded multiport memory arrays.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2005

A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.

[BibT_eX]

[DOI]

Arijit Raychowdhury

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.

[BibT_eX]

[DOI]