Swaroop Ghosh
Orcid: 0000-0001-8753-490X
According to our database1,
Swaroop Ghosh
authored at least 214 papers
between 2003 and 2024.
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Bibliography
2024
IEEE Des. Test, February, 2024
STIQ: Safeguarding Training and Inferencing of Quantum Neural Networks from Untrusted Cloud.
CoRR, 2024
Investigating impact of bit-flip errors in control electronics on quantum computation.
CoRR, 2024
CoRR, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024
Evaluating Efficacy of Model Stealing Attacks and Defenses on Quantum Neural Networks.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Q-Embroidery: A Study on Weaving Quantum Error Correction into the Fabric of Quantum Classifiers.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
AltGraph: Redesigning Quantum Circuits Using Generative Graph Models for Efficient Optimization.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
WEPRO: Weight Prediction for Efficient Optimization of Hybrid Quantum-Classical Algorithms.
CoRR, 2023
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays.
CoRR, 2023
Randomized Reversible Gate-Based Obfuscation for Secured Compilation of Quantum Circuit.
CoRR, 2023
IEEE Access, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
DeepQMLP: A Scalable Quantum-Classical Hybrid DeepNeural Network Architecture for Classification.
CoRR, 2022
IEEE Access, 2022
Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for Classification.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Robust and Secure Hybrid Quantum-Classical Computation on Untrusted Cloud-Based Quantum Hardware.
Proceedings of the 11th International Workshop on Hardware and Architectural Support for Security and Privacy, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Emerg. Top. Comput., 2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
CoRR, 2021
Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Reliab., 2020
IEEE Trans. Dependable Secur. Comput., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
CoRR, 2020
IEEE Access, 2020
Recent Advances in Emerging Technology-based Security Primitives, Attacks and Mitigation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the IEEE International Test Conference, 2020
Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection: (Invited Paper).
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Improving Reliability of Quantum True Random Number Generator using Machine Learning.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
Resiliency analysis and improvement of variational quantum factoring in superconducting qubit.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Analysis of crosstalk in NISQ devices and security implications in multi-programming regime.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
FAuto: An Efficient GMM-HMM FPGA Implementation for Behavior Estimation in Autonomous Systems.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the Computer Vision - ECCV 2020, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Emerg. Top. Comput., 2019
ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Analysis of Quantum Approximate Optimization Algorithm under Realistic Noise in Superconducting Qubits.
CoRR, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum Circuits.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Meeting the Conflicting Goals of Low-Power and Resiliency Using Emerging Memories : (Invited Paper).
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Device Research Conference, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques.
J. Low Power Electron., 2018
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.
ACM J. Emerg. Technol. Comput. Syst., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
J. Hardw. Syst. Secur., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
CoRR, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions.
Proc. IEEE, 2016
J. Low Power Electron., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
CoRR, 2016
Attack resilient architecture to replace embedded Flash with STTRAM in homogeneous IoTs.
CoRR, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.
Proc. IEEE, 2015
IEEE J. Solid State Circuits, 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
Schmitt-Trigger-based Recycling Sensor and Robust and High-Quality PUFs for Counterfeit IC Detection.
CoRR, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Novel self-calibrating recycling sensor using Schmitt-Trigger and voltage boosting for fine-grained detection.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Synergistic circuit and system design for energy-efficient and robust domain wall caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2011
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011
2010
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era.
Proc. IEEE, 2010
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
2008
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008
O<sup>2</sup>C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Instrum. Meas., 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Trans. Reliab., 2003