Swarnil Roy

According to our database, Swarnil Roy authored at least 4 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2019

Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.

Swarnil Roy, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose

IET Circuits Devices Syst., 2019

2018

Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET.

Sagar Mukherjee, Arka Dutta, Swarnil Roy, Chandan Kumar Sarkar

IEEE Trans. Circuits Syst. II Express Briefs, 2018

2016

Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance.

Sagar Mukherjee, Swarnil Roy, Arka Dutta, Chandan Kumar Sarkar

IET Circuits Devices Syst., 2016

2015

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET.

Sagar Mukherjee, Arka Dutta, Swarnil Roy, Kalyan Koley, Chandan Kumar Sarkar

Microelectron. J., 2015