Swarnalatha Radhakrishnan

According to our database, Swarnalatha Radhakrishnan authored at least 13 papers between 2004 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.

Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study.

Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose

CoRR, 2014

Loop Unrolling in Multi-pipeline ASIP Design.

Rajitha Navarathna, Swarnalatha Radhakrishnan, Roshan G. Ragel

CoRR, 2014

Axis2UNO: Web Services Enabled Openoffice.org.

B. A. N. M. Bambarasinghe, H. M. S. Huruggamuwa, Roshan G. Ragel, Swarnalatha Radhakrishnan

CoRR, 2014

2013

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors.

Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

DRMA: dynamically reconfigurable MPSoC architecture.

Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.

Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2013

2012

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.

Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2009

HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors.

Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic

IET Comput. Digit. Tech., 2009

2006

Heterogeneous multi-pipeline application specific instruction-set processor design and implementation.

Swarnalatha Radhakrishnan

PhD thesis, 2006

Customization of application specific heterogeneous multi-pipeline processors.

Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Application specific forwarding network and instruction encoding for multi-pipe ASIPs.

Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2004

Dual-pipeline heterogeneous ASIP design.

Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004