Svetlana V. Yarmolik

According to our database, Svetlana V. Yarmolik authored at least 13 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

Controlled method of random test synthesis.

Vyacheslav N. Yarmolik, Ireneusz Mrozek, Svetlana V. Yarmolik

Autom. Control. Comput. Sci., 2015

2014

Address sequences.

Vyacheslav N. Yarmolik, Svetlana V. Yarmolik

Autom. Control. Comput. Sci., 2014

2013

Generating modified Sobol sequences for multiple run march memory tests.

V. N. Yarmolik, S. V. Yarmolik

Autom. Control. Comput. Sci., 2013

Analyses of two run march tests with address decimation for BIST procedure.

Ireneusz Mrozek, Svetlana V. Yarmolik

Proceedings of the East-West Design & Test Symposium, 2013

2011

The synthesis of probability tests with a small number of kits.

S. V. Yarmolik, V. N. Yarmolik

Autom. Control. Comput. Sci., 2011

2010

Generalized adaptive signature analysis.

S. V. Yarmolik, Vyacheslav N. Yarmolik

Autom. Control. Comput. Sci., 2010

2009

Nondestructive RAM testing based on multiple signature comparison.

S. V. Yarmolik, V. N. Yarmolik

Autom. Control. Comput. Sci., 2009

2008

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests.

Svetlana V. Yarmolik

Int. J. Appl. Math. Comput. Sci., 2008

Determination of the optimal initial states for multiple-run RAM testing.

S. V. Yarmolik, Alexander N. Kurbatski, V. N. Yarmolik

Autom. Control. Comput. Sci., 2008

2007

Generation of address sequences for effective random access memory testing.

S. V. Yarmolik

Autom. Control. Comput. Sci., 2007

Address Sequences Generation for Multiple Run Memory Testing.

S. V. Yarmolik, Ireneusz Mrozek, Bartosz Sokol

Proceedings of the 6th International Conference on Computer Information Systems and Industrial Management Applications, 2007

2006

Address Sequences for March Tests to Detect Pattern Sensitive Faults.

Bartosz Sokol, S. V. Yarmolik

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Optimal Memory Address Seeds for Pattern Sensitive Faults Detection.

S. V. Yarmolik, Bartosz Sokol

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006