Sven Simon

Affiliations:
  • University of Stuttgart, Institute for Parallel and Distributed Systems, Germany


According to our database1, Sven Simon authored at least 75 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Multi-material blind beam hardening correction in near real-time based on non-linearity adjustment of projections.
J. Real Time Image Process., April, 2023

A resolution enhancement plug-in for deformable registration of medical images.
Biomed. Signal Process. Control., 2023

2022
An FPGA-Based Residual Recurrent Neural Network for Real-Time Video Super-Resolution.
IEEE Trans. Circuits Syst. Video Technol., 2022

3DVSR: 3D EPI volume-based approach for angular and spatial light field image super-resolution.
Signal Process., 2022

A GPU-accelerated light-field super-resolution framework based on mixed noise model and weighted regularization.
J. Real Time Image Process., 2022

FL-MISR: fast large-scale multi-image super-resolution for computed tomography based on multi-GPU acceleration.
J. Real Time Image Process., 2022

Computational scatter correction in near real-time with a fast Monte Carlo photon transport model for high-resolution flat-panel CT.
J. Real Time Image Process., 2022

2021
Bilateral Spectrum Weighted Total Variation for Noisy-Image Super-Resolution and Image Denoising.
IEEE Trans. Signal Process., 2021

GVLD: A Fast and Accurate GPU-Based Variational Light-Field Disparity Estimation Approach.
IEEE Trans. Circuits Syst. Video Technol., 2021

Making Historical Gyroscopes Alive - 2D and 3D Preservations by Sensor Fusion and Open Data Access.
Sensors, 2021

2020
Multi-frame super-resolution reconstruction based on mixed Poisson-Gaussian noise.
Signal Process. Image Commun., 2020

FDRN: A Fast Deformable Registration Network for Medical Images.
CoRR, 2020

2019
An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder.
J. Signal Process. Syst., 2019

A single-cycle parallel multi-slice connected components analysis hardware architecture.
J. Real Time Image Process., 2019

Architecture for parallel marker-free variable length streams decoding.
J. Real Time Image Process., 2019

Comparative Study and Proof of Single-Pass Connected Components Algorithms.
J. Math. Imaging Vis., 2019

A JND-Based Pixel-Domain Algorithm and Hardware Architecture for Perceptual Image Coding.
J. Imaging, 2019

Sub-Pixel Registration Technique for X-ray Phase Contrast Imaging.
Proceedings of the 2019 International Conference on Image and Vision Computing New Zealand, 2019

2018
Variational Disparity Estimation Framework for Plenoptic Image.
CoRR, 2018

GPU-Accelerated Light-Field Image Super-Resolution.
Proceedings of the 2018 International Conference on Advanced Computing and Applications, 2018

2017
Analyzing the Effect and Performance of Lossy Compression on Aeroacoustic Simulation of Gas Injector.
Comput., 2017

A resource-efficient monitoring architecture for hardware accelerated self-adaptive online data stream compression.
Proceedings of the Signal Processing: Algorithms, 2017

Variational disparity estimation framework for plenoptic images.
Proceedings of the 2017 IEEE International Conference on Multimedia and Expo, 2017

Light-field image compression based on variational disparity estimation and motion-compensated wavelet decomposition.
Proceedings of the 2017 IEEE International Conference on Image Processing, 2017

Hardware-based architecture for asymmetric numeral systems entropy decoder.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016
A Resource-Efficient Hardware Architecture for Connected Component Analysis.
IEEE Trans. Circuits Syst. Video Technol., 2016

Architecture for parallelizing decoding of marker-free variable length code streams.
Proceedings of the Signal Processing: Algorithms, 2016

Low complexity perceptual image coding by just-noticeable difference model based adaptive downsampling.
Proceedings of the 2016 Picture Coding Symposium, 2016

Online Bandwidth Reduction Using Dynamic Partial Reconfiguration.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Low Complexity Pixel Domain Perceptual Image Compression via Adaptive Down-Sampling.
Proceedings of the 2016 Data Compression Conference, 2016

2015
Visually lossless image compression extension for JPEG based on just-noticeable distortion evaluation.
Proceedings of the International Conference on Systems, Signals and Image Processing, 2015

High throughput hardware architectures for asymmetric numeral systems entropy coding.
Proceedings of the 9th International Symposium on Image and Signal Processing and Analysis, 2015

2014
Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Coding strategies and performance analysis of GPU accelerated image compression.
Proceedings of the 30th Picture Coding Symposium, 2013

A high-throughput FPGA architecture for parallel connected components analysis based on label reuse.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

High Throughput Coding of Video Signals.
Proceedings of the 2013 Data Compression Conference, 2013

Stream Processing of Scientific Big Data on Heterogeneous Platforms - Image Analytics on Big Data in Motion.
Proceedings of the 16th IEEE International Conference on Computational Science and Engineering, 2013

2012
Memory efficient lossless compression of image sequences with JPEG-LS and temporal prediction.
Proceedings of the 2012 Picture Coding Symposium, 2012

SSPQ - spatial domain perceptual image codec based on subsampling and perceptual quantization.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

On the JPEG 2000 ultrafast mode.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Correlation and convolution of image data using fermat number transform based on two's complement.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

Relaxation of particle image velocimetry based on single autocorrelation of filtered motion blurring.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

A memory-efficient parallel single pass architecture for connected component labeling of streamed images.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Fast lossless image compression with 2D Golomb parameter adaptation based on JPEG-LS.
Proceedings of the 20th European Signal Processing Conference, 2012

Fast and Context-Free Lossless Image Compression Algorithm Based on JPEG-LS.
Proceedings of the 2012 Data Compression Conference, Snowbird, UT, USA, April 10-12, 2012, 2012

2011
In Situ Power Analysis of General Purpose Graphical Processing Units.
Proceedings of the 19th International Euromicro Conference on Parallel, 2011

A memory efficient parallel lossless image compression engine for high performance embedded systems.
Proceedings of the 7th International Symposium on Image and Signal Processing and Analysis, 2011

On the numerical sensitivity of computer simulations on hybrid and parallel computing systems.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

Exploitation of context classification for parallel pixel coding in JPEG-LS.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

An image filter technique to relax particle image velocimetry.
Proceedings of the 19th European Signal Processing Conference, 2011

2010
Memory-efficient parallelization of JPEG-LS with relaxed context update.
Proceedings of the Picture Coding Symposium, 2010

2008
Using Arithmetic Coding for Reduction of Resulting Simulation Data Size on Massively Parallel GPGPUs.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 2008

Accelerating Simulations of Light Scattering Based on Finite-Difference Time-Domain Method with General Purpose GPUs.
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008

Acceleration of a finite-difference method with general purpose GPUs - Lesson learned.
Proceedings of 8th IEEE International Conference on Computer and Information Technology, 2008

2006
Low power synthesizable register files for processor and IP cores.
Integr., 2006

2005
Datenskalierung für die verlustleistungsarme Signalverarbeitung in Prozessorsystemen.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Power reduction of ASIPs by distributing the workload on several ASIP-instances.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

A power dissipation comparison of ALU-architectures for ASIPs.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004
Register Isolation for Synthesizable Register Files.
Proceedings of the Integrated Circuit and System Design, 2004

An instruction set for the efficient implementation of the CORDIC algorithm.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

The impact of clock gating schemes on the power dissipation of synthesizable register files.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A High-Speed Transceiver Architecture Implementable as Synthesizable IP Core.
Proceedings of the 2004 Design, 2004

2003
A power efficient register file architecture using master latch sharing.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Low power register file architecture for application specific DSPs.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
Low power transformation of datapath architectures with cyclic SFGs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms.
J. VLSI Signal Process., 1999

Low power datapath design using transformation similar to temporal localization of SFGs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Device level based cell modeling for fast power estimation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High-level circuit modeling for power estimation.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1997
Entwurf von Datenpfaden in schnellen integrierten Schaltungen.
PhD thesis, 1997

Low Power CORDIC Implementation Using Redundant Number Representation.
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1996
Built-in self test architectures for multistage interconnection networks.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Retiming of synchronous circuits with variable topology.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Retiming of Circuits Containing Multiplexers.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
A New Retiming Algorithm for Circuit Design.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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