Sven Reimer
According to our database1,
Sven Reimer
authored at least 17 papers
between 2011 and 2022.
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Bibliography
2022
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022
2018
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2018, 2018
2017
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2017
2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
PhD thesis, 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Automated Technology for Verification and Analysis, 2014
2013
Equivalence Checking for Partial Implementations Revisited.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013
Equivalence checking of partial designs using dependency quantified Boolean formulae.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Enhanced Integration of QBF Solving Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012
2011
Proceedings of the Design, Automation and Test in Europe, 2011