Sven-Ole Voigt

Orcid: 0000-0003-3258-1084

Affiliations:
  • Hamburg University of Technology, Germany


According to our database1, Sven-Ole Voigt authored at least 12 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of seven.
  • Erdős number3 of six.

Timeline

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Bibliography

2014
Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning.
Microprocess. Microsystems, 2014

2013
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs.
Int. J. Reconfigurable Comput., 2013

An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A multi-core FPGA-based SoC architecture with domain segregation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2011
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing.
J. Syst. Archit., 2010

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA.
Int. J. Reconfigurable Comput., 2010

A radix-10 digit recurrence division unit with a constant digit selection function.
Proceedings of the 28th International Conference on Computer Design, 2010

An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2008
Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platforms.
PhD thesis, 2008

Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA Platforms.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

2007
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms.
Proceedings of the FPL 2007, 2007


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