Sven Gesper

Orcid: 0000-0002-3570-1638

According to our database1, Sven Gesper authored at least 8 papers between 2019 and 2024.

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Bibliography

2024
Multi-Level Prototyping of a Vertical Vector AI Processing System.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

N<sup>2</sup>V<sup>2</sup>PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture.
Proceedings of the 13th IEEE International Conference on Consumer Electronics - Berlin, 2023


Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2021
Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments.
Int. J. Parallel Program., 2021

2019
Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019


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