Sven Beyer

According to our database, Sven Beyer authored at least 23 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate.

Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni

CoRR, 2024

Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out.

Omkar Phadke, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Shimeng Yu

Proceedings of the IEEE International Reliability Physics Symposium, 2024

Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG.

Ralf Richter, Stefan Dünkel, Bert Müller, Frank Mauersberger, Sven Wittek, Sven Beyer, Jana Böhme, Uwe Ritter, Violetta Sessi, Zhen Xu, Maximilian Drescher, Jinho Kim, Parviz Ghazavi, Yuri Tkachev, Latt Tee, Zonglin Li, Mandana Tadayoni, Fan Luo, Nhan Do, Serguei Jourba, Catherine Decobert, Gilles Festes, Bruno Villard, Thibaut Pate-Cazal

Proceedings of the IEEE International Memory Workshop, 2024

Charge trapping challenges of CMOS embedded complementary FeFETs.

Sven Beyer, Dominik Kleimaier, Stefan Dünkel, Halid Mulaosmanovic, Steven Soss, Johannes Müller, Zhouhang Jiang, Kai Ni, Thomas Mikolajick, Haidi Zhou

Proceedings of the IEEE International Memory Workshop, 2024

2023

Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator.

Vivek Parmar, Franz Müller, Jing-Hua Hsuen, Sandeep Kaur Kingra, Nellie Laleni, Yannick Raffel, Maximilian Lederer, Alptekin Vardar, Konrad Seidel, Taha Soliman, Tobias Kirchner, Tarek Ali, Stefan Dünkel, Sven Beyer, Tian-Li Wu, Sourav De, Manan Suri, Thomas Kämpfe

Adv. Intell. Syst., June, 2023

Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.

Paritosh Meihar, Rowtu Srinu, Sandip Lashkare, Ajay Kumar Singh, Halid Mulaosmanovic, Veeresh Deshpande, Stefan Dünkel, Sven Beyer, Udayan Ganguly

CoRR, 2023

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni

CoRR, 2023

FeFET-based MirrorBit cell for High-density NVM storage.

Paritosh Meihar, Rowtu Srinu, Vivek Saraswat, Sandip Lashkare, Halid Mulaosmanovic, Stefan Dünkel, Sven Beyer, Udayan Ganguly

CoRR, 2023

Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications.

Franz Müller, Sourav De, Maximilian Lederer, Raik Hoffmann, Ricardo Olivo, Thomas Kämpfe, Konrad Seidel, Tarek Ali, Halid Mulaosmanovic, Stefan Dünkel, Johannes Müller, Sven Beyer, Gerald Gerlach

Proceedings of the IEEE International Memory Workshop, 2023

2022

Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.

Yixin Xu, Zijian Zhao, Yi Xiao, Tongguang Yu, Halid Mulaosmanovic, Dominik Kleimaier, Stefan Dünkel, Sven Beyer, Xiao Gong, Rajiv V. Joshi, X. Sharon Hu, Shixian Wen, Amanda Sofie Rios, Kiran Lekkala, Laurent Itti, Eric Homan, Sumitha George, Vijaykrishnan Narayanan, Kai Ni

CoRR, 2022

Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window.

Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Endurance improvements and defect characterization in ferroelectric FETs through interface fluorination.

Yannick Raffel, Ricardo Olivo, Maximilian Lederer, Franz Müller, Raik Hoffmann, Tarek Ali, Konstantin Mertens, Luca Pirro, Maximilian Drescher, Sven Beyer, Thomas Kämpfe, Konrad Seidel, Lukas M. Eng, Johannes Heitmann

Proceedings of the IEEE International Memory Workshop, 2022

Interfacial Layer Engineering to Enhance Noise Immunity of FeFETs for IMC Applications.

Yannick Raffel, Sunanda Thunder, Maximilian Lederer, Ricardo Olivo, Raik Hoffmann, Luca Pirro, Sven Beyer, Talha Chohan, Po-Tsang Huang, Sourav De, Thomas Kämpfe, Konrad Seidel, Johannes Heitmann

Proceedings of the International Conference on IC Design and Technology, 2022

2021

Hardware Functional Obfuscation With Ferroelectric Active Interconnects.

Tongguang Yu, Yixin Xu, Shan Deng, Zijian Zhao, Nicholas Jao, You Sung Kim, Stefan Dünkel, Sven Beyer, Kai Ni, Sumitha George, Vijaykrishnan Narayanan

CoRR, 2021

Novel embedded single poly floating gate flash demonstrated in 22nm FDSOI technology.

Thomas Melde, Martin Trentzsch, Stefan Dünkel, Ralf Richter, Michael Otto, H. Giesler, Francois Weisbuch, N. Weddeler, Sven Beyer

Proceedings of the IEEE International Memory Workshop, 2021

2019

Performance Improvement on HfO2-Based 1T Ferroelectric NVM by Electrical Preconditioning.

Carlo Cagli, Luca Perniola, Fred Gaillard, Stefan Dünkel, Thomas Melde, B. Mueller, Martin Trentzsch, Sven Wittek, Sven Beyer

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.

Evelyn T. Breyer, Halid Mulaosmanovic, Jens Trommer, Thomas Melde, Stefan Dünkel, Martin Trentzsch, Sven Beyer, Thomas Mikolajick, Stefan Slesazeck

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2010

Automated formal verification of processors based on architectural models.

Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009

Generating an Efficient Instruction Set Simulator from a Complete Property Suite.

Ulrich Kühne, Sven Beyer, Christian Pichler

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

2006

Putting it all together - Formal verification of the VAMP.

Sven Beyer, Christian Jacobi, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul

Int. J. Softw. Tools Technol. Transf., 2006

2005

Putting it all together: formal verification of the VAMP.

Sven Beyer

PhD thesis, 2005

Towards the Formal Verification of Lower System Layers in Automotive Systems.

Sven Beyer, Peter Böhm, Michael Gerke, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2003

Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.

Sven Beyer, Christian Jacobi, Daniel Kroening, Dirk Leinenbach, Wolfgang J. Paul

Proceedings of the Correct Hardware Design and Verification Methods, 2003