Suvadeep Banerjee
Orcid: 0000-0001-5188-1651
According to our database1,
Suvadeep Banerjee
authored at least 41 papers
between 2011 and 2024.
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Bibliography
2024
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning.
CoRR, 2024
Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators.
IEEE Trans. Computers, August, 2023
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, April, 2023
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits.
Proceedings of the IEEE International Test Conference, 2023
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Special Session: Effective In-field Testing of Deep Neural Network Hardware Accelerators.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Proceedings of the IEEE International Test Conference, 2022
Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Real-Time Error Detection in Nonlinear Control Systems Using Machine Learning Assisted State-Space Encoding.
IEEE Trans. Dependable Secur. Comput., 2021
CoRR, 2021
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State Checksums.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
2019
ALERA: Accelerated Reinforcement Learning Driven Adaptation to Electro-Mechanical Degradation in Nonlinear Control Systems Using Encoded State Space Error Signatures.
ACM Trans. Intell. Syst. Technol., 2019
Mixed Signal Design Validation Using Reinforcement Learning Guided Stimulus Generation for Behavior Discovery.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
2018
PhD thesis, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks.
Proceedings of the 23rd IEEE European Test Symposium, 2018
2017
On-line diagnosis and compensation for parametric failures in linear state variable circuits and systems using time-domain checksum observers.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Probabilistic error detection and correction in switched capacitor circuits using checksum codes.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Real-time self-learning for control law adaptation in nonlinear systems using encoded check states.
Proceedings of the 22nd IEEE European Test Symposium, 2017
2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Checksum based error detection in linearized representations of non linear control systems.
Proceedings of the 17th Latin-American Test Symposium, 2016
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states.
Proceedings of the 2016 IEEE International Test Conference, 2016
Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
Proceedings of the 28th International Conference on VLSI Design, 2015
Concurrent error detection in nonlinear digital filters using checksum linearization and residue prediction.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
2014
Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Design of low cost fault tolerant analog circuits using real-time learned error compensation.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Enhanced Resolution Time-Domain Reflectometry for High Speed Channels: Characterizing Spatial Discontinuities with Non-ideal Stimulus.
Proceedings of the 22nd Asian Test Symposium, 2013
2011
Feedback linearizing indirect adaptive fuzzy control with foraging based on-line plant model estimation.
Appl. Soft Comput., 2011