Susumu Hatano

According to our database1, Susumu Hatano authored at least 2 papers between 1991 and 2001.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

1992
1994
1996
1998
2000
0
1
2
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2001
High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface.
Proceedings of the Ninth Symposium on High Performance Interconnects, 2001

1991
Design of a second-level cache chip for shared-bus multimicroprocessor systems.
IEEE J. Solid State Circuits, April, 1991


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