Susmita Sur-Kolay
Orcid: 0000-0002-2052-3779
According to our database1,
Susmita Sur-Kolay
authored at least 128 papers
between 1988 and 2024.
Collaborative distances:
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Bibliography
2024
SN Comput. Sci., December, 2024
Intermediate qutrit-assisted Toffoli gate decomposition with quantum error correction.
Quantum Inf. Process., February, 2024
FragQC: An efficient quantum error reduction technique using quantum circuit fragmentation.
J. Syst. Softw., 2024
CoRR, 2024
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs.
CoRR, 2024
CoRR, 2024
Panoptic Segmentation and Labelling of Lumbar Spine Vertebrae using Modified Attention Unet.
CoRR, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the International Symposium on Secure and Private Execution Environment Design, 2024
Machine Learning based Decoding of Heavy Hexagonal QECC for Asymmetric Quantum Noise.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
J. Multiple Valued Log. Soft Comput., 2023
Integr., 2023
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.
CoRR, 2023
CoRR, 2023
Proceedings of the Computer Vision and Image Processing - 8th International Conference, 2023
2022
Quantum Inf. Process., 2022
Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.
CoRR, 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs.
Proceedings of the IEEE International Test Conference, 2022
2021
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud.
ACM Trans. Embed. Comput. Syst., 2021
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments.
IET Circuits Devices Syst., 2021
FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs.
CoRR, 2021
Proceedings of the 36th International Conference on Image and Vision Computing New Zealand, 2021
2020
IET Image Process., 2020
Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate.
CoRR, 2020
CoRR, 2020
Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive Crossbar.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
2019
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Fault Coverage of a Test Set on Structure-Preserving Siblings of a Circuit-Under-Test.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2018
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning.
CoRR, 2018
CoRR, 2018
CoRR, 2018
2017
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.
IEEE Trans. Multi Scale Comput. Syst., 2017
IEEE Trans. Multi Scale Comput. Syst., 2017
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the Reversible Computation - 9th International Conference, 2017
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
IEEE Trans. Emerg. Top. Comput., 2016
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip.
IET Comput. Digit. Tech., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Multi Scale Comput. Syst., 2015
IEEE J. Biomed. Health Informatics, 2015
J. Multiple Valued Log. Soft Comput., 2015
Inf. Process. Lett., 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
J. Low Power Electron., 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the Distributed Computing and Internet Technology, 2014
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
2012
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the IEEE 25th International SOC Conference, 2012
2011
VLSI Design, 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IET Comput. Digit. Tech., 2011
CoRR, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
2010
IET Comput. Digit. Tech., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
2009
ACM Trans. Embed. Comput. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Int. J. Bioinform. Res. Appl., 2009
Appl. Soft Comput., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
2008
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007
Proceedings of the 10th International Conference on Information Technology, 2007
2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI.
Proceedings of the 9th International Conference in Information Technology, 2006
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Pattern Recognition and Machine Intelligence, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
ACM Trans. Design Autom. Electr. Syst., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Distributed Computing, 2004
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit.
Proceedings of the 2004 Design, 2004
2003
Flavours of Traveling Salesman Problem in VLSI Design.
Proceedings of the 1st Indian International Conference on Artificial Intelligence, 2003
2001
ACM Trans. Design Autom. Electr. Syst., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001
2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 2000 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
1997
Proceedings of the 1997 International Symposium on Physical Design, 1997
1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
A unified approach to topology generation and area optimization of general floorplans.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1995
1992
Proceedings of the 29th Design Automation Conference, 1992
1991
The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1988
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1988