Sushrant Monga

According to our database, Sushrant Monga authored at least 7 papers between 2011 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

A variable interval enhanced jitter tolerant programmable bandwidth blind-oversampling CDR for multi-gigabit rates.

Sushrant Monga, Shouri Chatterjee

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOS.

Sushrant Monga, Shouri Chatterjee

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 µm CMOS.

Sushrant Monga, Shouri Chatterjee

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

An inductorless continuous time equalizer with programmability for gigabit links.

Sushrant Monga, Shouri Chatterjee

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

Adaptive driver with automatic sense and calibration in CMOS 40LP.

Sushrant Monga

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2012

High speed stress tolerant 1.6 V - 3.6 V low to high voltage CMOS level shift architecture in 40 nm.

Sushrant Monga

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS.

Sushrant Monga, Vinod Kumar

Proceedings of the 37th European Solid-State Circuits Conference, 2011