Sushil Sakhare

According to our database1, Sushil Sakhare authored at least 8 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

SRAM designs for 5nm node and beyond: Opportunities and challenges.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2015
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of interconnect multiple-patterning variability on SRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014


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