Susheel J. Chandra

According to our database, Susheel J. Chandra authored at least 8 papers between 1987 and 1991.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1991

Use of CrossCheck test technology in practical applications.

Susheel J. Chandra, Tushar Gheewala, Hector R. Sucar, George Swan

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

ATPG Based on a Novel Grid-Addressable Latch Element.

Susheel J. Chandra, Tom Ferry, Tushar Gheewala, Kerry Pierce

Proceedings of the 28th Design Automation Conference, 1991

1989

Techniques to speedup test generation for VLSI circuits

Susheel J. Chandra

PhD thesis, 1989

Experimental evaluation of testability measures for test generation (logic circuits).

Susheel J. Chandra, Janak H. Patel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

High performance test generation for accurate defect models in CMOS gate array technology.

Hector R. Sucar, Susheel J. Chandra, David J. Wharton

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Accurate logic simulation in the presence of unknowns.

Susheel J. Chandra, Janak H. Patel

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Test generation in a parallel processing environment.

Susheel J. Chandra, Janak H. Patel

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987

A Hierarchical Approach Test Vector Generation.

Susheel J. Chandra, Janak H. Patel

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987