Susana Patón

Orcid: 0000-0003-0911-2642

According to our database1, Susana Patón authored at least 44 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

System Analysis of Capacitance-to-Digital Converters Based on a Switched-Capacitor Feedback.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

A 3<sup>rd</sup>-order Noise Shaped Multistage Open-Loop Current Controlled Oscillator-based ADC with Non-Linearity Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A Gray-Encoded Ring Oscillator for Efficient Frequency-to-Digital Conversion in VCO-Based ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022
An Analysis of Noise in Multi-Bit ΣΔ Modulators with Low-Frequency Input Signals.
Sensors, 2022

Optimal reconfiguration instant in ΣΔ Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2020
Low Power Phase-Encoded MAC Accelerator for Smart Sensors with VCO-based ADCs.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Model of Continuous-Time Sigma Delta Modulation Based on Pulse Frequency Encoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

DAC mismatch shaping in Discrete Time Sigma Delta ADCs with non uniform quantizer.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019
Clock Jitter Analysis of Continuous-Time ΣΔ Modulators Based on a Relative Time-Base Projection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Idle Tones Reduction in Digital Single-Bit ΣΔ Modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Continuous Time Sigma-Delta Modulator with VCO-based integrators and optimized NTF zeros.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
VCO-ADC Resolution Enhancement Using Maximum Length Sequences.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shaping.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2016
Signal boosting to extend the bandwidth of oversampled converters.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
A noise coupled ΣΔ architecture using a Non Uniform Quantizer.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2014
Time difference amplifiers to improve the dynamic range of MASH time encoded ADCs.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A 0.03mm<sup>2</sup>, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
A multi-stage and time-based continuous time ΣΔ Architecture using a Gated Ring Oscillator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A distortion corrected passive RC noise shaping ADC for biomedical applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Analysis of VCO based noise shaping ADCs linearized by PWM modulation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm <sup>2</sup> 65 nm CMOS Circuit.
IEEE J. Solid State Circuits, 2011

2010
Continuous Time Cascade Sigma Delta Modulator without digital cancellation filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A time encoded decimation filter for noise shaped power DACs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 0.08 mm2, 7mW Time-Encoding Oversampling Converter with 10 bits and 20MHz BW in 65nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 0.1 mm<sup>2</sup>, Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2009

Second-order multi-bit ΣΔ ADC using a Pulse-Width Modulated DAC and an integrating quantizer.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
An A/D converter based on pulse width modulation and the walsh-hadamard transform.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Resolution enhancement of sigma-delta modulators using a tracking digital filter.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006
Spectral shaping of clock jitter errors for continuous time sigma-delta modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 2-2 Discrete Time Cascaded ΣΔ Modulator With NTF Zero Using Interstage Feedback.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Design of Cascaded Continuous-Time Sigma-Delta Modulators.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Synthesis of sigma delta modulators employing continuous time delays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution.
IEEE J. Solid State Circuits, 2004

Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A jitter insensitive continuous-time ΣΔ modulator using transmission lines.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Continuous time sigma-delta modulators with transmission line resonators and improved jitter and excess loop delay performance.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS.
Proceedings of the ESSCIRC 2003, 2003

2002
A superregenerative receiver for phase and frequency modulated carriers.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999
A continuous-time noise-shaping modulator for logarithmic A/D conversion.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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