Surya Narayanan

According to our database, Surya Narayanan authored at least 11 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration.

Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2020

SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks.

Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon

Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019

Wire-Aware Architecture and Dataflow for CNN Accelerators.

Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

A Case for Dynamic Activation Quantization in CNNs.

Karl Taht, Surya Narayanan, Rajeev Balasubramonian

Proceedings of the 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2018

Moving CNN Accelerator Computations Closer to Data.

Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian

Proceedings of the 1st Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2018

2017

INXS: Bridging the throughput and energy gap for spiking neural networks.

Surya Narayanan, Ali Shafiee, Rajeev Balasubramonian

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2015

Sequential and Parallel Code Sections are Different: they may require different Processors.

Surya Narayanan, André Seznec

Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

An empirical high level performance model for future many-cores.

Surya Narayanan, Bharath Narasimha Swamy, André Seznec

Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

2014

Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era.

Surya Narayanan, Bharath Narasimha Swamy, André Seznec

Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, 2014

2011

Communication service for hardware tasks executed on dynamic and partial reconfigurable resources.

Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Hardware OS Communication Service and Dynamic Memory Management for RSoCs.

Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011