Suruchi Sharma

Orcid: 0000-0002-0561-6862

According to our database1, Suruchi Sharma authored at least 8 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2024
Controllability-Constrained Deep Network Models for Enhanced Control of Dynamical Systems.
Proceedings of the American Control Conference, 2024

2021
Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET.
IET Circuits Devices Syst., 2021

Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

DC and linearity performance of a novel Si0.6Ge0.4/Ge Dopingless Tunnel FET for ultra-low voltage applications.
Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

2020
Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction.
IET Circuits Devices Syst., 2020

Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

Performance analysis of Pocket Doped Junction-Less TFET.
Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2015
Design of Dependable Task Scheduling Algorithm in Cloud Environment.
Proceedings of the Third International Symposium on Women in Computing and Informatics, 2015


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