Suriyaprakash Natarajan

According to our database, Suriyaprakash Natarajan authored at least 54 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack.

Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024

Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning.

Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu

CoRR, 2024

Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors.

Suhas Krishna Kashyap, Chinmaye Raghavendra, Suriyaprakash Natarajan, Sule Ozev

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

Generating Storage-Aware Test Sets Targeting Several Fault Models.

Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems.

Sanjay Das, Shamik Kundu, Pooja Madhusoodhanan, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriya Natarajan, Kanad Basu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators.

Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Fei Su, Suriyaprakash Natarajan, Kanad Basu

IEEE Trans. Computers, August, 2023

A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators.

Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators.

Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu

IEEE Des. Test, April, 2023

Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits.

Ayush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu

Proceedings of the IEEE International Test Conference, 2023

2022

DEFCON: Defect Acceleration through Content Optimization.

Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee

Proceedings of the IEEE International Test Conference, 2022

A defect tolerance framework for improving yield.

Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.

Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman

Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021

Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators.

Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu

IEEE Trans. Very Large Scale Integr. Syst., 2021

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts.

Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators.

Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020

Automated Design For Yield Through Defect Tolerance.

Suriyaprakash Natarajan, Andres F. Malavasi, Pascal Andreas Meinerzhagen

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization.

Srikanth Venkataraman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang

Proceedings of the IEEE International Test Conference, 2020

SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.

Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee

Proceedings of the IEEE International Test Conference, 2020

2019

Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.

Sujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee

Proceedings of the IEEE International Test Conference, 2019

2017

A novel test compression algorithm for analog circuits to decrease production costs.

Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan

Integr., 2017

Innovative practices session 3C hardware security.

Jeyavijayan (JV) Rajendran, Peilin Song, Suriya Natarajan

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Innovative practices session 4C data analytics in test.

Suriya Natarajan, Abhijit Sathaye

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays.

Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Session 4B - Panel data analytics in semiconductor manufacturing.

Suriyaprakash Natarajan, Li-C. Wang

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Infant mortality tests for analog and mixed-signal circuits.

Suvadeep Banerjee, Suriyaprakash Natarajan

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Fault simulation for analog test coverage.

Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary

Proceedings of the 2016 IEEE International Test Conference, 2016

Every test makes a difference: Compressing analog tests to decrease production costs.

Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Innovative practices session 7C: Mixed signal test and debug.

Suriya Natarajan

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts?

Sreekumar V. Kodakara, Suriya Natarajan

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Identifying DC bias conditions for maximum DC current in digitally-assisted analog design.

Chong Li, Suriyaprakash Natarajan, Chuanjin Richard Shi

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Fast eye diagram analysis for high-speed CMOS circuits.

Seyed Nematollah Ahmadyan, Chenjie Gu, Suriyaprakash Natarajan, Eli Chiprout, Shobha Vasudevan

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.

Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Hot topic session 9C: Test and fault tolerance for emerging memory technologies.

Suriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Innovative practices session 4C: Disruptive solutions in the non-digital world.

Amitava Majumdar, Suriya Natarajan, Stephen K. Sunter, Prashant Goteti, Ke Huang

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.

Ali Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris

Proceedings of the 2014 International Test Conference, 2014

2013

Special session 12B: Panel post-silicon validation & test in huge variance era.

Takahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity.

Helia Naeimi, Suriya Natarajan, Kushagra Vaid, Prabhakar Kudva, Mahesh Natu

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Framework for analog test coverage.

Debesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue

Proceedings of the International Symposium on Quality Electronic Design, 2013

Scalable and efficient analog parametric fault identification.

Mustafa Berke Yelten, Suriyaprakash Natarajan, Bin Xue, Prashant Goteti

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2011

The bang for the buck with resiliency: Yield or field?

Arani Sinha, Suriyaprakash Natarajan

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

The buck stops with wafer test: Dream or reality?

Suriyaprakash Natarajan, Arani Sinha

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

2010

Innovative practices session 9C: Implications of power delivery network for validation and testing.

Suriyaprakash Natarajan

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Path coverage based functional test generation for processor marginality validation.

Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche

Proceedings of the 2011 IEEE International Test Conference, 2010

2008

Case Study on Speed Failure Causes in a Microprocessor.

Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani

IEEE Des. Test Comput., 2008

On Accelerating Path Delay Fault Simulation of Long Test Sequences.

I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta

Proceedings of the 2008 IEEE International Test Conference, 2008

On efficient generation of instruction sequences to test for delay defects in a processor.

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

The Region-Exhaustive Fault Model.

Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil

Proceedings of the 16th Asian Test Symposium, 2007

2006

Path Delay Fault Simulation on Large Industrial Designs.

Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Selecting High-Quality Delay Tests for Manufacturing Test and Debug.

Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005

Untestable Multi-Cycle Path Delay Faults in Industrial Designs.

Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2002

XIDEN: Crosstalk Target Identification Framework.

Shahin Nazarian, Hang Huang, Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Switch-level delay test of domino logic circuits.

Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1999

Switch-level delay test.

Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Process Variations and their Impact on Circuit Operation.

Suriyaprakash Natarajan, Melvin A. Breuer, Sandeep K. Gupta

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998