Suriyaprakash Natarajan
According to our database1,
Suriyaprakash Natarajan
authored at least 53 papers
between 1998 and 2024.
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Bibliography
2024
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning.
CoRR, 2024
Structural Built In Self Test of Analog Circuits using ON/OFF Keying and Delay Monitors.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators.
IEEE Trans. Computers, August, 2023
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, April, 2023
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits.
Proceedings of the IEEE International Test Conference, 2023
2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization.
Proceedings of the IEEE International Test Conference, 2020
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts.
Proceedings of the IEEE International Test Conference, 2020
2019
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology.
Proceedings of the IEEE International Test Conference, 2019
2017
Integr., 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
2016
Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Every test makes a difference: Compressing analog tests to decrease production costs.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Identifying DC bias conditions for maximum DC current in digitally-assisted analog design.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation.
Proceedings of the 2014 International Test Conference, 2014
2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivity.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
2010
Innovative practices session 9C: Implications of power delivery network for validation and testing.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
2008
Proceedings of the 2008 IEEE International Test Conference, 2008
On efficient generation of instruction sequences to test for delay defects in a processor.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998