Suresh Ramalingam

According to our database, Suresh Ramalingam authored at least 7 papers between 2012 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Enabling Chiplet Integration Beyond 7nm (Invited).

Suresh Ramalingam

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

CCECE 2021 Invited Paper: Holistic Performance, Reliability and Thermal Understanding of HPC Real Utilization on Silicon Architecture.

Gamal Refai-Ahmed, Hoa Do, I-Ru Chen, Jae-Gyung Ahn, Huayan Wang, Xin Wu, Suresh Ramalingam

Proceedings of the 34th IEEE Canadian Conference on Electrical and Computer Engineering, 2021

2016

HBM package integration: Technology trends, challenges and applications.

Suresh Ramalingam

Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications.

Kang Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi

Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2013

Interconnect and package design of a heterogeneous stacked-silicon FPGA.

Ephrem Wu, Khaldoon Abugharbieh, Bahareh Banijamali, Suresh Ramalingam, Paul Wu, Chris Wyland

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

FPGAs with 28Gb/s transceivers built with heterogeneous stacked-silicon interconnects.

Ephrem Wu, Suresh Ramalingam

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

Advancing high performance heterogeneous integration through die stacking.

Liam Madden, Ephrem Wu, Namhoon Kim, Bahareh Banijamali, Khaldoon Abugharbieh, Suresh Ramalingam, Xin Wu

Proceedings of the 38th European Solid-State Circuit conference, 2012