Surajit Kumar Roy

Integr., January, 2024

2023

Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection.

[BibT_eX]

[DOI]

J. Electron. Test., August, 2023

Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation.

[BibT_eX]

[DOI]

Sourav Ghosh

J. Electron. Test., February, 2023

Cost Effective Single Target Sample Preparation on Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Sourav Ghosh

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

2022

Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation.

[BibT_eX]

[DOI]

Microelectron. J., 2022

A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

2021

TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Hardware Trojan Horse Detection through Improved Switching of Dormant Nets.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets.

[BibT_eX]

[DOI]

Sourav Ghosh

J. Electron. Test., 2021

2020

Hardware Trojan Detection Using Improved Testability Measures.

[BibT_eX]

[DOI]

Priyanka Naskar

Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Devices, Circuits and Systems, 2020

2019

Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Hardware Trojan Detection by Stimulating Transitions in Rare Nets.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Iterative Parallel Test to Detect and Diagnose Multiple Defects for Digital Microfluidic Biochip.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Identification of Faulty TSVs in 3D IC During Pre-Bond Testing.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Identification of Faulty TSV with a Built-In Self-Test Mechanism.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Faulty TSVs Identification in 3D IC Using Pre-bond Testing.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Modeling and Analysis of Transient Heat for 3D IC.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Design-for-test and test time optimization for 3D SOCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

TSV repairing for 3D ICs using redundant TSV.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

2016

Optimization of Test Wrapper for TSV Based 3D SOCs.

[BibT_eX]

[DOI]

Hafizur Rahaman

J. Electron. Test., 2016

2015

Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips.

[BibT_eX]

[DOI]

Hafizur Rahaman

IET Comput. Digit. Tech., 2015

A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Recovery of faulty TSVs in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Test Time Optimization for 3D-SICs Having Multiple Towers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

Session Based Core Test Scheduling for 3D SOCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013

Power constraints test scheduling of 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.

[BibT_eX]

[DOI]

Hafizur Rahaman

Proceedings of the 8th International Design and Test Symposium, 2013

Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Post-bond Stack Testing for 3D Stacked IC.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Testing 3D stacked ICs for post-bond partial/complete stack.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing.

[BibT_eX]

[DOI]

Sobitri Chatterjee