Suraj Sindia

According to our database1, Suraj Sindia authored at least 18 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests.
J. Electron. Test., 2015

Innovative practices session 2C: New technologies, new challenges - 2.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2014
A Test Time Theorem and its Applications.
J. Electron. Test., 2014

Specification test minimization for given defect level.
Proceedings of the 15th Latin American Test Workshop, 2014

2013
Neural Network Guided Spatial Fault Resilience in Array Processors.
J. Electron. Test., 2013

Finding best voltage and frequency to shorten power-constrained test time.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

High sensitivity test signatures for unconventional analog circuit test paradigms.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients.
J. Electron. Test., 2012

Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing.
J. Electron. Test., 2012

Towards spatial fault resilience in array processors.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Impact of process variations on computers used for image processing.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Tailoring Tests for Functional Binning of Integrated Circuits.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Testing linear and non-linear analog circuits using moment generating functions.
Proceedings of the 12th Latin American Test Workshop, 2011

Test and Diagnosis of Analog Circuits Using Moment Generating Functions.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Polynomial coefficient based DC testing of non-linear analog circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients.
Proceedings of the Eighteentgh Asian Test Symposium, 2009


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