Suraj Mandal
Orcid: 0000-0002-2855-6559
According to our database1,
Suraj Mandal
authored at least 7 papers
between 2019 and 2024.
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2024
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Bibliography
2024
Winograd for NTT: A Case Study on Higher-Radix and Low-Latency Implementation of NTT for Post Quantum Cryptography on FPGA.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024
KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023
2022
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT.
ACM Trans. Design Autom. Electr. Syst., 2022
2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019