Suraj Mandal

According to our database, Suraj Mandal authored at least 6 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA.

Suraj Mandal, Debapriya Basu Roy

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design.

Suraj Mandal, Debapriya Basu Roy

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2023

A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA.

Harish Prasad Allam, Suraj Mandal, Debapriya Basu Roy

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022

Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT.

Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen, Rajat Subhra Chakraborty

ACM Trans. Design Autom. Electr. Syst., 2022

2019

A Novel Test Vector Generation Method for Hardware Trojan Detection.

Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

An Efficient Implementation of Arbiter PUF on FPGA for IoT Application.

Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019