Supreeth Mysore Shivanandamurthy

According to our database1, Supreeth Mysore Shivanandamurthy authored at least 4 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2021
ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM.
CoRR, 2021

ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2019
A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019


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