Supratik Chakraborty

Orcid: 0000-0002-7527-7675

Affiliations:
  • IIT Bombay, Mumbai, India


According to our database1, Supratik Chakraborty authored at least 95 papers between 1993 and 2024.

Collaborative distances:

Timeline

1995
2000
2005
2010
2015
2020
0
5
10
1
1
3
2
2
2
1
1
1
2
1
2
2
1
1
1
2
1
7
4
3
3
3
4
1
4
3
4
4
5
1
2
1
2
1
1
1
1
2
3
1
1
3
3

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
Tractable representations for Boolean functional synthesis.
Ann. Math. Artif. Intell., October, 2024

A shallow dive into the depths of non-termination checking for C programs.
CoRR, 2024

Network Inversion of Binarised Neural Nets.
CoRR, 2024

Weakest Precondition Inference for Non-Deterministic Linear Array Programs.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

PROTON: PRObes for Termination Or Not (Competition Contribution).
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

On Dependent Variables in Reactive Synthesis.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2024

Automated Synthesis of Decision Lists for Polynomial Specifications over Integers.
Proceedings of the LPAR 2024: Proceedings of 25th Conference on Logic for Programming, 2024

Practical Approximate Quantifier Elimination for Non-linear Real Arithmetic.
Proceedings of the Formal Methods - 26th International Symposium, 2024

Auditable Algorithms for Approximate Model Counting.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

Exact ASP Counting with Compact Encodings.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
VeriAbsL: Scalable Verification by Abstraction and Strategy Prediction (Competition Contribution).
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2023

Learning Monitor Ensembles for Operational Design Domains.
Proceedings of the Runtime Verification - 23rd International Conference, 2023

Boolean Functional Synthesis: From Under the Hood of Solvers.
Proceedings of the Logic and Its Applications - 10th Indian Conference, 2023

Counterexample Guided Knowledge Compilation for Boolean Functional Synthesis.
Proceedings of the Computer Aided Verification - 35th International Conference, 2023

2022
Functional synthesis via input-output separation.
Formal Methods Syst. Des., April, 2022

Full-program induction: verifying array programs sans loop invariants.
Int. J. Softw. Tools Technol. Transf., 2022

On Synthesizing Computable Skolem Functions for First Order Logic.
Proceedings of the 47th International Symposium on Mathematical Foundations of Computer Science, 2022

On Eventual Non-negativity and Positivity for the Weighted Sum of Powers of Matrices.
Proceedings of the Automated Reasoning - 11th International Joint Conference, 2022

Projected Model Counting: Beyond Independent Support.
Proceedings of the Automated Technology for Verification and Analysis, 2022

2021
Approximate Model Counting.
Proceedings of the Handbook of Satisfiability - Second Edition, 2021

Boolean functional synthesis: hardness and practical algorithms.
Formal Methods Syst. Des., 2021

On synthesizing Skolem functions for first order logic formulae.
CoRR, 2021

A Normal Form Characterization for Efficient Boolean Skolem Function Synthesis.
Proceedings of the 36th Annual ACM/IEEE Symposium on Logic in Computer Science, 2021

Synthesizing Pareto-Optimal Interpretations for Black-Box Models.
Proceedings of the Formal Methods in Computer Aided Design, 2021

Diffy: Inductive Reasoning of Array Programs Using Difference Invariants.
Proceedings of the Computer Aided Verification - 33rd International Conference, 2021

2020
Bidirectionality in flow-sensitive demand-driven analysis.
Sci. Comput. Program., 2020

On Uniformly Sampling Traces of a Transition System (Extended Version).
CoRR, 2020

Verifying Array Manipulating Programs with Full-Program Induction.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2020

VeriAbs : Verification by Abstraction and Test Generation (Competition Contribution).
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2020

On Uniformly Sampling Traces of a Transition System.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
Highlights of software R&D in India.
Commun. ACM, 2019

Knowledge Compilation for Boolean Functional Synthesis.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

On Symbolic Approaches for Computing the Matrix Permanent.
Proceedings of the Principles and Practice of Constraint Programming, 2019

Functional Significance Checking in Noisy Gene Regulatory Networks.
Proceedings of the Principles and Practice of Constraint Programming, 2019

On the Hardness of Probabilistic Inference Relaxations.
Proceedings of the Thirty-Third AAAI Conference on Artificial Intelligence, 2019

2018
Demand-driven Alias Analysis : Formalizing Bidirectional Analyses for Soundness and Precision.
CoRR, 2018

What's Hard About Boolean Functional Synthesis?
Proceedings of the Computer Aided Verification - 30th International Conference, 2018

2017
Symbolic trajectory evaluation for word-level verification: theory and implementation.
Formal Methods Syst. Des., 2017

Matching Multiplications in Bit-Vector Formulas.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

Towards Parallel Boolean Functional Synthesis.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2017

Verifying Array Manipulating Programs by Tiling.
Proceedings of the Static Analysis - 24th International Symposium, 2017

On Petri Nets with Hierarchical Special Arcs.
Proceedings of the 28th International Conference on Concurrency Theory, 2017

2016
A layered algorithm for quantifier elimination from linear modular constraints.
Formal Methods Syst. Des., 2016

A generalization of the Łoś-Tarski preservation theorem.
Ann. Pure Appl. Log., 2016

Algorithmic Improvements in Approximate Counting for Probabilistic Inference: From Linear to Logarithmic SAT Calls.
Proceedings of the Twenty-Fifth International Joint Conference on Artificial Intelligence, 2016

Constrained Sampling and Counting: Universal Hashing Meets SAT Solving.
Proceedings of the Beyond NP, 2016

Approximate Probabilistic Inference via Word-Level Counting.
Proceedings of the Thirtieth AAAI Conference on Artificial Intelligence, 2016

2015
On Parallel Scalable Uniform SAT Witness Generation.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

From Weighted to Unweighted Model Counting.
Proceedings of the Twenty-Fourth International Joint Conference on Artificial Intelligence, 2015

Skolem Functions for Factored Formulas.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Word-Level Symbolic Trajectory Evaluation.
Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014
A Generalization of the Łoś-Tarski Preservation Theorem over Classes of Finite Structures.
Proceedings of the Mathematical Foundations of Computer Science 2014, 2014

Quantifier Elimination for Linear Modular Constraints.
Proceedings of the Mathematical Software - ICMS 2014, 2014

Balancing Scalability and Uniformity in SAT Witness Generator.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Distribution-Aware Sampling and Weighted Model Counting for SAT.
Proceedings of the Twenty-Eighth AAAI Conference on Artificial Intelligence, 2014

2013
Generalizations of the Los-Tarski Preservation Theorem
CoRR, 2013

Extending Quantifier Elimination to Linear Inequalities on Bit-Vectors.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2013

A Scalable Approximate Model Counter.
Proceedings of the Principles and Practice of Constraint Programming, 2013

A Scalable and Nearly Uniform Generator of SAT Witnesses.
Proceedings of the Computer Aided Verification - 25th International Conference, 2013

Improving approximate reachability by dynamic interleavings of projections-based algorithms.
Proceedings of the 2013 IEEE International Symposium on Computer-Aided Control System Design, 2013

Improved Upper and Lower Bounds for Büchi Disambiguation.
Proceedings of the Automated Technology for Verification and Analysis, 2013

2012
Preservation under Substructures modulo Bounded Cores.
Proceedings of the Logic, Language, Information and Computation, 2012

Reasoning about Heap Manipulating Programs using Automata Techniques.
Proceedings of the Modern Applications of Automata Theory., 2012

2011
Bottom-up shape analysis using LISF.
ACM Trans. Program. Lang. Syst., 2011

Determinization of $\omega$-automata unified
CoRR, 2011

Frontmatter, Table of Contents, Preface, Conference Organization, External Reviewers.
Proceedings of the IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, 2011

A Quantifier Elimination Algorithm for Linear Modular Equations and Disequations.
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2010
Refining abstract interpretations.
Inf. Process. Lett., 2010

On Semantic Generalizations of the Bernays-Schönfinkel-Ramsey Class with Finite or Co-finite Spectra
CoRR, 2010

Bounding Variance and Expectation of Longest Path Lengths in DAGs.
Proceedings of the Twenty-First Annual ACM-SIAM Symposium on Discrete Algorithms, 2010

2009
Bottom-Up Shape Analysis.
Proceedings of the Static Analysis, 16th International Symposium, 2009

On Minimal Odd Rankings for Büchi Complementation.
Proceedings of the Automated Technology for Verification and Analysis, 2009

2008
Efficient guided symbolic reachability using reachability expressions.
Int. J. Softw. Tools Technol. Transf., 2008

Automatically Refining Abstract Interpretations.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2008

2007
A Scalable Symbolic Simulator for Verilog RTL.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

2006
Reasoning about synchronization in GALS systems.
Formal Methods Syst. Des., 2006

Interface Design for Rationally Clocked GALS Systems.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
Bounded Validity Checking of Interval Duration Logic.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2005

2004
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2002
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Layout-Driven Timing Optimization by Generalized De Morgan Transform.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
Complexity Of Minimum-Delay Gate Resizing.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000
A self-timed real-time sorting network.
IEEE Trans. Very Large Scale Integr. Syst., 2000

1999
Timing analysis of asynchronous systems using time separation of events.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Min-max timing analysis and an application to asynchronous circuits.
Proc. IEEE, 1999

1998
Practical timing analysis of asynchronous circuits using time separation of events.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997
Approximate algorithms for time separation of events.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Timing Analysis of Extended Burst-Mode Circuits.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

More Accurate Polynomial-Time Min-Max Timing Simulation.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996
Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines.
IEEE Trans. Computers, 1996

1993
Delay Fault Test Generation with Cellular Automata.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Synthesis of Self-Checking Sequential Machines Using Cellular Automata.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Cellular automata based synthesis of easily and fully testable FSMs.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993


  Loading...