Sunmean Kim

According to our database, Sunmean Kim authored at least 15 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

Trends and Challenges in Computing-in-Memory for Neural Network Model: A Review From Device Design to Application-Side Optimization.

Ke Yu, Sunmean Kim, Jun Rim Choi

IEEE Access, 2024

2023

Optimizing Ternary Multiplier Design With Fast Ternary Adder.

Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

2022

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.

Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Low-Power Ternary Multiplication Using Approximate Computing.

Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Memcapacitor based Minimum and Maximum Gate Design.

Jiyoung Min, Sunmean Kim, Seokhyeong Kang

Proceedings of the 18th International SoC Design Conference, 2021

Ternary Sense Amplifier Design for Ternary SRAM.

Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang

Proceedings of the 18th International SoC Design Conference, 2021

Design and Analysis of a Low-Power Ternary SRAM.

Youngchang Choi, Sunmean Kim, Kyongsu Lee, Seokhyeong Kang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits.

Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion.

Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang

Proceedings of the International SoC Design Conference, 2020

MTCMOS-based Ternary to Binary Converter.

Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang

Proceedings of the International SoC Design Conference, 2020

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction.

Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019

Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU.

Sunghye Park, Sunmean Kim, Seokhyeong Kang

Proceedings of the 2019 International SoC Design Conference, 2019

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm.

Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.

Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018

An optimal gate design for the synthesis of ternary logic circuits.

Sunmean Kim, Taeho Lim, Seokhyeong Kang

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018