Sunmean Kim

Orcid: 0000-0001-8240-5658

According to our database1, Sunmean Kim authored at least 14 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Optimizing Ternary Multiplier Design With Fast Ternary Adder.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

2022
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Low-Power Ternary Multiplication Using Approximate Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Memcapacitor based Minimum and Maximum Gate Design.
Proceedings of the 18th International SoC Design Conference, 2021

Ternary Sense Amplifier Design for Ternary SRAM.
Proceedings of the 18th International SoC Design Conference, 2021

Design and Analysis of a Low-Power Ternary SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion.
Proceedings of the International SoC Design Conference, 2020

MTCMOS-based Ternary to Binary Converter.
Proceedings of the International SoC Design Conference, 2020

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU.
Proceedings of the 2019 International SoC Design Conference, 2019

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018
An optimal gate design for the synthesis of ternary logic circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018


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