Sunil Shukla

Proceedings of the 7th International Conference on Computing, Communication and Security, 2022

2021

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

Efficient AI System Design With Cross-Layer Approximate Computing.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2018

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Across the Stack Opportunities for Deep Learning Acceleration.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2017

Accelerator Design for Deep Learning Training: Extended Abstract: Invited.

[BibT_eX]

[DOI]

Ankur Agrawal

Chia-Yu Chen

Jungwook Choi

Kailash Gopalakrishnan

Jinwook Oh

Viji Srinivasan

Swagath Venkataramani

Wei Zhang

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Approximate computing: Challenges and opportunities.

[BibT_eX]

[DOI]

Ankur Agrawal

Jungwook Choi

Kailash Gopalakrishnan

Vijayalakshmi Srinivasan

Zehra Sura

Proceedings of the IEEE International Conference on Rebooting Computing, 2016

2015

Growing a Software Language for Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the 1st Summit on Advances in Programming Languages, 2015

Cycle-Accurate Replay and Debugging of Running FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

2014

Parallel real-time garbage collection of multiple heaps in reconfigurable hardware.

[BibT_eX]

[DOI]

Perry Cheng

Proceedings of the International Symposium on Memory Management, 2014

2013

QUKU: A dual-layer reconfigurable architecture.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

FPGA Programming for the Masses.

[BibT_eX]

[DOI]

Rodric M. Rabbah

ACM Queue, 2013

And then there were none: a stall-free real-time garbage collector for reconfigurable hardware.

[BibT_eX]

[DOI]

Perry Cheng

Commun. ACM, 2013

The Liquid Metal IP bridge.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

A compiler and runtime for heterogeneous computing.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

FPGA-based combined architecture for stream categorization and intrusion detection.

[BibT_eX]

[DOI]

Rodric M. Rabbah

Martin Vorbach

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

Improving intelligibility of synthesized speech in noise with emphasized prosody.

[BibT_eX]

[DOI]

Proceedings of the Third Workshop on Experimental Linguistics, 2010

2008

QUKU: A Mixed Grain Dynamically Reconfigurable Architecture for High Performance Computing

[BibT_eX]

[DOI]

PhD thesis, 2008

A Web Server Based Edge Detector Implementation in FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007

Improving High Quality Concatenative Text-to-Speech Using the Circular Linear Prediction Model.

[BibT_eX]

[DOI]

PhD thesis, 2007

QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks.

[BibT_eX]

[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Improving High Quality TTS using Circular Linear Prediction and Constant Pitch Transform.

[BibT_eX]

[DOI]

Thomas P. Barnwell III

Proceedings of the IEEE International Conference on Acoustics, 2007

2006

QUKU: A Two-Level Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.

[BibT_eX]

[DOI]

Reiner W. Hartenstein

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

QUKU: A Coarse Grained Paradigm for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006, 2006

QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2004

Single bit error correction implementation in CRC-16 on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

2002

A Fault Modeling Technique to Test Memory BIST Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Circular LPC modeling and constant pitch transform for accurate speech analysis and high quality speech synthesis.

[BibT_eX]

[DOI]