Sunil Rafeeque

According to our database, Sunil Rafeeque authored at least 6 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2024

A Novel Channel-Aware, Non-Sampling UART With Augmented Clock Frequency Resilience.

Timothy Simon Thomas, Arun Singh, Shyam Ramanathan, Sunil Rafeeque

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2005

A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters.

Sunil Rafeeque, Vinita Vasudevan

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.

Sunil Rafeeque, Vinita Vasudevan

J. Electron. Test., 2004

A Built-in-Self-Test Scheme for Digital to Analog Converters.

Sunil Rafeeque, Vinita Vasudevan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC.

Sunil Rafeeque, Vinita Vasudevan

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

Area efficient current steering DAC using current tuning.

Sunil Rafeeque

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002