Sunil Rafeeque

Orcid: 0009-0004-6999-3423

According to our database1, Sunil Rafeeque authored at least 6 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of six.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A Novel Channel-Aware, Non-Sampling UART With Augmented Clock Frequency Resilience.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

2005
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.
J. Electron. Test., 2004

A Built-in-Self-Test Scheme for Digital to Analog Converters.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002
Area efficient current steering DAC using current tuning.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002


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