Sunil P. Khatri

IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator.

[BibT_eX]

[DOI]

Cheng-Yen Lee

Sarma B. K. Vrudhula

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Scaled Population Division for Approximate Computing.

[BibT_eX]

[DOI]

Kunal Bharathi

Jiang Hu

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

An Extremely Low-voltage Floating Gate Artificial Neuron.

[BibT_eX]

[DOI]

Kyler R. Scott

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Hardware Validation Framework for a Networked Dynamic Multi-factor Security Protocol.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Advanced Communication Technologies and Networking, 2023

2022

A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Flash-based Digital to Analog Converter for Low Power Applications.

[BibT_eX]

[DOI]

Kyler R. Scott

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations.

[BibT_eX]

[DOI]

Chan-Wei Hu

Jiang Hu

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

A Flash-based Current-mode IC to Realize Quantized Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Hardware Acceleration of Hash Operations in Modern Microprocessors.

[BibT_eX]

[DOI]

Viacheslav V. Fedorov

IEEE Trans. Computers, 2021

CIDAN: Computing in DRAM with Artificial Neurons.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020

A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking.

[BibT_eX]

[DOI]

Prasenjit Biswas

Sarit Pal

Proceedings of the 3rd International Conference on Information and Computer Technologies, 2020

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells.

[BibT_eX]

[DOI]

Ankit Wagle

Sarma B. K. Vrudhula

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Scaled Population Subtraction for Approximate Computing.

[BibT_eX]

[DOI]

Kunal Bharathi

Jiang Hu

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Scaled Population Arithmetic for Efficient Stochastic Computing.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Fast, Ring-Based Design of 3-D Stacked DRAM.

[BibT_eX]

[DOI]

Andrew J. Douglass

IEEE Trans. Very Large Scale Integr. Syst., 2019

Threshold Logic in a Flash.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

A GPU-CPU heterogeneous algorithm for NGS read alignment.

[BibT_eX]

[DOI]

Ahmad Al Kawam

Aniruddha Datta

Int. J. Comput. Biol. Drug Des., 2018

Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications.

[BibT_eX]

[DOI]

Andrew J. Douglass

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

A Homomorphic Encryption Scheme Based on Affine Transforms.

[BibT_eX]

[DOI]

Kyle Loyka

He Zhou

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing.

[BibT_eX]

[DOI]

Ahmad Al Kawam

Aniruddha Datta

IEEE ACM Trans. Comput. Biol. Bioinform., 2017

An FPGA-Based Coprocessor for Hash Unit Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Fast, Ring-Based Design of 3D Stacked DRAM.

[BibT_eX]

[DOI]

Andrew J. Douglass

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A Robust C-element Design with Enhanced Metastability Performance.

[BibT_eX]

[DOI]

Kinshuk Sharma

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design of a Flash-based Circuit for Multi-valued Logic.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

2016

FTCAM: An Area-Efficient Flash-Based Ternary CAM Design.

[BibT_eX]

[DOI]

Viacheslav V. Fedorov

IEEE Trans. Computers, 2016

Response to "Comment on 'Zero and negative energy dissipation at information-theoretic erasure'".

[BibT_eX]

[DOI]

Claes-Goran Granqvist

Ferdinand Peper

CoRR, 2016

A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A novel hardware hash unit design for modern microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Exploring static and dynamic flash-based FPGA design topologies.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Implementing low power digital circuits using flash devices.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A flash-based digital circuit design flow.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A GPU-based implementation of a sensor tasking methodology.

[BibT_eX]

[DOI]

Suman Chakravorty

Proceedings of the 19th International Conference on Information Fusion, 2016

A practical methodology to validate the statistical behavior of bloom filters.

[BibT_eX]

[DOI]

Venkateshwar Kottapalli

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.

[BibT_eX]

[DOI]

Mohammadmahdi R. Yousefi

Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015

Zero and negative energy dissipation at information-theoretic erasure.

[BibT_eX]

[DOI]

Claes-Göran Granqvist

Ferdinand Peper

CoRR, 2015

Exploring the viability of stochastic computing.

[BibT_eX]

[DOI]

Joao Marcos de Aguiar

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

An Efficient Approach to Sample On-Chip Power Supplies.

[BibT_eX]

[DOI]

Luke Murray

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation.

[BibT_eX]

[DOI]

Kun Bian

D. M. H. Walker

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

An area-efficient Ternary CAM design using floating gate transistors.

[BibT_eX]

[DOI]

Viacheslav V. Fedorov

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

An asynchronous Network-on-Chip router with low standby power.

[BibT_eX]

[DOI]

Amr Elshennawy

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A comparison of FinFET based FPGA LUT designs.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Look-up Table Design for Deep Sub-threshold through Full-Supply Operation.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

Using GPUs to Accelerate CAD Algorithms.

[BibT_eX]

[DOI]

John F. Croix

IEEE Des. Test, 2013

A low-jitter phase-locked resonant clock generation and distribution scheme.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Noise-based algorithms for functional equivalence and tautology checking.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A source-synchronous Htree-based network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector.

[BibT_eX]

[DOI]

Amr Elshennawy

Craig M. Marianno

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

GPU implementation of a scalable non-linear congruential generator for cryptography applications.

[BibT_eX]

[DOI]

Aditya Belsare

Steve Liu

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Mixed structural-functional path delay test generation and compaction.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Exploring topologies for source-synchronous ring-based network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Crosstalk avoidance codes for 3D VLSI.

[BibT_eX]

[DOI]

Rajeev Kumar

S. M. Hossein Tabatabaei Yazdi

Proceedings of the Design, Automation and Test in Europe, 2013

2012

On Optimal and Achievable Fix-Free Codes.

[BibT_eX]

[DOI]

Serap A. Savari

Navid Abedini

Subramanian Poothamkurissi Swaminathan

IEEE Trans. Inf. Theory, 2012

Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design.

[BibT_eX]

[DOI]

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT.

[BibT_eX]

[DOI]

Rajeev Kumar

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Alleviating NBTI-induced failure in off-chip output drivers.

[BibT_eX]

[DOI]

Bhavitavya Bhadviya

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Determining gene function in boolean networks using boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2012 IEEE International Workshop on Genomic Signal Processing and Statistics, 2012

A fast, source-synchronous ring-based network-on-chip design.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Boolean satisfiability using noise based logic.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Application of logic synthesis to the understanding and cure of genetic diseases.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications.

[BibT_eX]

[DOI]

Didem Zeliha Turker

Edgar Sánchez-Sinencio

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Noise-based Deterministic Logic and Computing: a Brief Survey.

[BibT_eX]

[DOI]

Int. J. Unconv. Comput., 2011

Noise-based information processing: Noise-based logic and computing: what do we have so far?

[BibT_eX]

[DOI]

CoRR, 2011

Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

An Automated Approach for Minimum Jitter Buffered H-Tree Construction.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

A novel cryptographic key exchange scheme using resistors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Workshop on Genomic Signal Processing and Statistics, 2011

2010

A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Fault Table Computation on GPUs.

[BibT_eX]

[DOI]

J. Electron. Test., 2010

Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel

[BibT_eX]

[DOI]

Tamás Horváth

CoRR, 2010

Instantaneous noise-based logic

[BibT_eX]

[DOI]

Ferdinand Peper

CoRR, 2010

Towards brain-inspired computing

[BibT_eX]

[DOI]

Zoltan Gingl

CoRR, 2010

An efficient pulse flip-flop based launch-on-shift scan cell.

[BibT_eX]

[DOI]

Rajesh Kumar

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Boolean satisfiability on a graphics processor.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Inference of gene predictor set using Boolean satisfiability.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Workshop on Genomic Signal Processing and Statistics, 2010

A SAT-Based Scheme to Determine Optimal Fix-Free Codes.

[BibT_eX]

[DOI]

Navid Abedini

Serap A. Savari

Proceedings of the 2010 Data Compression Conference (DCC 2010), 2010

Implementing digital logic with sinusoidal supplies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations.

[BibT_eX]

[DOI]

Suganth Paul

IEEE Trans. Very Large Scale Integr. Syst., 2009

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Efficient On-Chip Crosstalk Avoidance CODEC Design.

[BibT_eX]

[DOI]

Victor H. Cordero Calle

IEEE Trans. Very Large Scale Integr. Syst., 2009

FPGA-based hardware acceleration for Boolean satisfiability.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization.

[BibT_eX]

[DOI]

Sasidharan Ekambavanan

Krishna R. Narayanan

J. Low Power Electron., 2009

Selective Forward Body Bias for High Speed and Low Power SRAMs.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Noise-Based Logic and Computing: From Boolean Logic Gates to Brain Circuitry and Its Possible Hardware Realization.

[BibT_eX]

[DOI]

Proceedings of the Natural Computing - 4th International Workshop on Natural Computing, 2009

Design and implementation of a sub-threshold BFSK transmitter.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

SEU hardened clock regeneration circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation.

[BibT_eX]

[DOI]

Srikanth Alaparthi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A radiation tolerant Phase Locked Loop design for digital electronics.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

A robust pulsed flip-flop and its use in enhanced scan design.

[BibT_eX]

[DOI]

Rajesh Kumar

Tarun Soni

Proceedings of the 27th International Conference on Computer Design, 2009

A PLL design based on a standing wave resonant oscillator.

[BibT_eX]

[DOI]

Vinay Karkala

Proceedings of the 27th International Conference on Computer Design, 2009

3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

On-chip bidirectional wiring for heavily pipelined systems using network coding.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Computer Design, 2009

Introduction to GPU programming for EDA.

[BibT_eX]

[DOI]

John F. Croix

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Fault table generation using Graphics Processing Units.

[BibT_eX]

[DOI]

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

Robust window-based multi-node technology-independent logic minimization.

[BibT_eX]

[DOI]

Jeff L. Cobb

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Low power and high performance sram design using bank-based selective forward body bias.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Closed-loop modeling of power and temperature profiles of FPGAs.

[BibT_eX]

[DOI]

Peng Li

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Accelerating statistical static timing analysis using graphics processing units.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Fast circuit simulation on graphics processing units.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Efficient analytical determination of the SEU-induced pulse shape.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Highly parallel decoding of space-time codes on graphics processing units.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual Allerton Conference on Communication, 2009

2008

Dynamically De-Skewable Clock Distribution Methodology.

[BibT_eX]

[DOI]

Arjun Kapoor

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

SAT-based ATPG using multilevel compatible don't-cares.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Resource sharing among mutually exclusive sum-of-product blocks for area reduction.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

A Timing-Driven Approach to Synthesize Fast Barrel Shifters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations.

[BibT_eX]

[DOI]

Integr., 2008

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).

[BibT_eX]

[DOI]

Peng Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A novel, highly SEU tolerant digital circuit design approach.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Computer Design, 2008

A robust, fast pulsed flip-flop design.

[BibT_eX]

[DOI]

Arunprasad Venkatraman

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Pipelined network of PLA based circuit design.

[BibT_eX]

[DOI]

Suganth Paul

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Improving FPGA routability using network coding.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A lithography-friendly structured ASIC design approach.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.

[BibT_eX]

[DOI]

Charu Nagpal

Proceedings of the Design, Automation and Test in Europe, 2008

A Single-supply True Voltage Level Shifter.

[BibT_eX]

[DOI]

Gagandeep Mallarapu

Proceedings of the Design, Automation and Test in Europe, 2008

Energy Efficient and High Speed On-Chip Ternary Bus.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Clock Distribution Scheme using Coplanar Transmission Lines.

[BibT_eX]

[DOI]

Victor H. Cordero Calle

Proceedings of the Design, Automation and Test in Europe, 2008

Towards acceleration of fault simulation using graphics processing units.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

A fast, analytical estimator for the SEU-induced pulse width in combinational designs.

[BibT_eX]

[DOI]

Charu Nagpal

Proceedings of the 45th Design Automation Conference, 2008

Forbidden transition free crosstalk avoidance CODEC design.

[BibT_eX]

[DOI]

Chengyu Zhu

Proceedings of the 45th Design Automation Conference, 2008

2007

High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

A Predictably Low-Leakage ASIC Design Style.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

A methodology for interconnect dimension determination.

[BibT_eX]

[DOI]

Jeff L. Cobb

Proceedings of the 2007 International Symposium on Physical Design, 2007

A Structured ASIC Design Approach Using Pass Transistor Logic.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Toggle Equivalence Preserving (TEP) Logic Optimization.

[BibT_eX]

[DOI]

Eugene Goldberg

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

An algorithm to minimize leakage through simultaneous input vector control and circuit modification.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Efficient don't care computation for hierarchical designs.

[BibT_eX]

[DOI]

M. Lovell

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A probabilistic method to determine the minimum leakage vector for combinational designs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Generalized buffering of PTL logic stages using Boolean division.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Computing during supply voltage switching in DVS enabled real-time processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Memory-based crosstalk canceling CODECs for on-chip buses.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Efficient, Scalable Hardware Engine for Boolean SATisfiability.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

CMOS Comparators for High-Speed and Low-Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

On the Improvement of Statistical Static Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Network coding for routability improvement in VLSI.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Implementation of MOSFET based capacitors for digital applications.

[BibT_eX]

[DOI]

Bo Shen

Takis Zourntos

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A design flow to optimize circuit delay by using standard cells and PLAs.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Resource and delay efficient matrix multiplication using newer FPGA devices.

[BibT_eX]

[DOI]

Scott J. Campbell

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A PLA based asynchronous micropipelining approach for subthreshold circuit design.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A design approach for radiation-hard digital electronics.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Controlling inductive cross-talk and power in off-chip buses using CODECs.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Non-Manhattan Routing Using a Manhattan Router.

[BibT_eX]

[DOI]

Edward Hursey

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Efficient SAT-based combinational ATPG using multi-level don't-cares.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Performance model for inter-chip communication considering inductive cross-talk and cost.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Broadband Impedance Matching for Inductive Interconnect in VLSI Packages.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Minimum Energy Near-threshold Network of PLA based Design.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

X-Routing using Two Manhattan Route Instances.

[BibT_eX]

[DOI]

Seraj Ahmad

Vijay Balasubramanian

Edward Hursey

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Practical techniques to reduce skew and its variations in buffered clock networks.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A Boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks.

[BibT_eX]

[DOI]

John Valavi

Proceedings of IEEE International Conference on Communications, 2005

Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

A variation tolerant subthreshold design approach.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents.

[BibT_eX]

[DOI]

Sandeep Dhar

Proceedings of the 42nd Design Automation Conference, 2005

A dynamic voltage scaling algorithm for energy reduction in hard real-time systems.

[BibT_eX]

[DOI]

Van R. Culver

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

SPFD-based wire removal in standard-cell and network-of-PLA circuits.

[BibT_eX]

[DOI]

Subarnarekha Sinha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A novel clock distribution and dynamic de-skewing methodology.

[BibT_eX]

[DOI]

Arjun Kapoor

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A metal and via maskset programmable VLSI design methodology using PLAs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High-throughput VLSI implementations of iterative decoders and related code construction problems.

[BibT_eX]

[DOI]

Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

Exploiting Crosstalk to Speed up On-Chip Buse.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A robust algorithm for approximate compatible observability don't care (CODC) computation.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

IP routing table compression using ESPRESSO-MV.

[BibT_eX]

[DOI]

Jianjian Bian

Proceedings of the 11th IEEE International Conference on Networks, 2003

A fast ternary CAM design for IP networking applications.

[BibT_eX]

[DOI]

Bruce Gamache

Zachary Pfeffer

Proceedings of the 12th International Conference on Computer Communications and Networks, 2003

2002

An efficient and regular routing methodology for datapath designsusing net regularity extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

A regularity-driven fast gridless detailed router for high frequency datapath designs.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement.

[BibT_eX]

[DOI]

Wilsin Gosti

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Analysis and avoidance of cross-talk in on-chip buses.

[BibT_eX]

[DOI]

Anup Tirumala

Proceedings of the Ninth Symposium on High Performance Interconnects, 2001

2000

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks.

[BibT_eX]

[DOI]

Subarnarekha Sinha

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999

Sequential Multi-Valued Network Simplification using Redundancy Removal.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Multi-Valued Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

A Novel VLSI Layout Fabric for Deep Sub-Micron Applications.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1996

A study of composition schemes for mixed apply/compose based construction of ROBDDs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Decomposition Techniques for Efficient ROBDD Construction.

[BibT_eX]

[DOI]

Masahiro Fujita

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

VIS.

[BibT_eX]

[DOI]

Gary D. Hachtel

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

Engineering Change in a Non-Deterministic FSM Setting.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

VIS: A System for Verification and Synthesis.

[BibT_eX]

[DOI]

Gary D. Hachtel