Sunil D. Sherlekar

According to our database, Sunil D. Sherlekar authored at least 27 papers between 1988 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Intel Many Integrated Core (MIC) Architecture.

Sunil D. Sherlekar

Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

Parallel Computing Goes Mainstream.

Sunil D. Sherlekar

Proceedings of the Contemporary Computing - 5th International Conference, 2012

2003

A Global Access Independent Billing Model: Users' Perspective.

Sunil D. Sherlekar, Rajeev Prasad

Wirel. Pers. Commun., 2003

2000

Power Reduction Techniques for Portable DSP Applications.

Mahesh Mehendale, Sunil D. Sherlekar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

Low Power Code Generation of Multiplication-free Linear Transforms.

Mahesh Mehendale, Sunil D. Sherlekar

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998

Low-power realization of FIR filters on programmable DSPs.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

IEEE Trans. Very Large Scale Integr. Syst., 1998

Extensions to Programmable DSP architectures for Reduced Power Dissipation.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters.

Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Low Power Realization of FIR Filters Implemented using Distributed Arithmetic.

Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar

Proceedings of the ASP-DAC '98, 1998

1997

Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Monitoring machine based synthesis technique for concurrent error detection in finite state machines.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

J. Electron. Test., 1996

Low power realization of FIR filters using multirate architectures.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Optimized Code Generation of Multiplication-free Linear Transforms.

Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar

Proceedings of the 33st Conference on Design Automation, 1996

1995

Concurrent Error Detection Using Monitoring Machines.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

IEEE Des. Test Comput., 1995

A new methodology for the design of low-cost fail safe circuits and networks.

B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Synthesis of multiplier-less FIR filters with minimum number of additions.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Techniques for low power realization for FIR filters.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993

Export of VLSI Design and CAD: Present and Future.

Sunil D. Sherlekar

Proceedings of the Sixth International Conference on VLSI Design, 1993

State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

A Behavioral Fault Simulator for Ideal.

Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran

IEEE Des. Test Comput., 1992

A Behavioral Fault Simulator For Ideal.

Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the Fifth International Conference on VLSI Design, 1992

Path breaker: a tool for the optimal design of speed independent asynchronous controllers.

Yogesh Mishra, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the conference on European design automation, 1992

1991

A methodology for the design of SFS/SCD circuits for a class of unordered codes.

Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh

J. Electron. Test., 1991

A Methodology for Designing Optimal Self-Checking Sequential Circuits.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1989

Ideas: a tool for VLSI CAD.

Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar

IEEE Des. Test, 1989

1988

Conditionally robust two-pattern tests and CMOS design for testability.

Sunil D. Sherlekar, P. S. Subramanian

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988