Sungkyung Park

Affiliations:
  • Pusan National University, Department of Electronics Engineering, Korea


According to our database1, Sungkyung Park authored at least 23 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Design Space Exploration of FFT Accelerators for IEEE 802.11ax using High-Level Synthesis.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2022
Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows.
IEEE Access, 2022

Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs.
IEEE Access, 2022

Optimization of Multi-Core Accelerator Performance Based on Accurate Performance Estimation.
IEEE Access, 2022

Optimization of Scatter Network Architectures and Bank Allocations for Sparse CNN Accelerators.
IEEE Access, 2022

2021
Optimization of Communication Schemes for DMA-Controlled Accelerators.
IEEE Access, 2021

Design and Implementation of a Digital Front-End With Digital Compensation for Low-Complexity 4G Radio Transceivers.
IEEE Access, 2021

System-Level Communication Performance Estimation for DMA-Controlled Accelerators.
IEEE Access, 2021

2020
Transaction-level Model Simulator for Communication-Limited Accelerators.
CoRR, 2020

Roofline-Model-Based Design Space Exploration for Dataflow Techniques of CNN Accelerators.
IEEE Access, 2020

2019
Latency-Insensitive Controller for Convolutional Neural Network Accelerators.
Proceedings of the 2019 International SoC Design Conference, 2019

Spatial Data Dependence Graph Simulator for Convolutional Neural Network Accelerators.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Optimizations of Scatter Network for Sparse CNN Accelerators.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2017
Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications.
J. Circuits Syst. Comput., 2017

2016
Quantization Noise Analysis of Time-to-Digital-Converter-Based All-Digital Phase-Locked Loop and Frequency Discriminators.
J. Circuits Syst. Comput., 2016

High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms.
J. Circuits Syst. Comput., 2016

CSD-based CORDIC algorithm and its VLSI implementation.
IEICE Electron. Express, 2016

Impact of power amplifier configuration on LTE carrier aggregation performance.
IEICE Electron. Express, 2016

Analysis of RSRP Measurement Accuracy.
IEEE Commun. Lett., 2016

2015
Decimation Chain Modeling for Dual-Band Radio Receiver and Its Operation for Continuous Packet Connectivity.
J. Inform. and Commun. Convergence Engineering, 2015

2012
Digital Compensation of IQ Imbalance for Dual-Carrier Double Conversion Receivers.
IEICE Trans. Commun., 2012

A Fractional-N PLL with Dual-Mode Detector and Counter.
IEICE Trans. Electron., 2012

2011
On Soft Decision Value Calculation for Linear-Dispersion Codes with SC-FDMA.
IEEE Trans. Wirel. Commun., 2011


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