Sungju Ryu
Orcid: 0000-0002-0254-391X
According to our database1,
Sungju Ryu
authored at least 21 papers
between 2016 and 2024.
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Bibliography
2024
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024
Statues: Energy-Efficient Video Object Detection on Edge Security Devices with Computational Skipping.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
2023
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
IEICE Electron. Express, December, 2023
Teleport: A High-Performance ShiftNet Hardware Accelerator with Fused Layer Computation.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
2022
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks.
IEEE J. Solid State Circuits, 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
IEEE J. Solid State Circuits, 2021
Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines.
IEICE Electron. Express, 2019
CoRR, 2019
BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
2016
Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016