Sungho Kang
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Known people with the same name:
- Sungho Kang 001 (Yonsei University, Department of Electrical and Electronic Engineering, Computer Systems Reliable SoC Laboratory, Seoul, Korea)
- Sungho Kang 002 (Sungkyunkwan University, Department of Electrical and Computer Engineering, Seoul, South Korea)
Bibliography
2020
Analysis of Electroencephalography Signals on the Contents of Cognitive Function Game: Attention and Memory.
J. Medical Imaging Health Informatics, 2020
2017
Test item priority estimation for high parallel test efficiency under ATE debug time constraints.
Proceedings of the International Test Conference in Asia, 2017
2016
A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
2014
Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEICE Electron. Express, 2014
2013
Bit transmission error correction scheme for FlexRay based automotive communication systems.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
2011
Path search engine for fast optimal path search using efficient hardware architecture.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEICE Trans. Inf. Syst., 2010
2009
A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
2008
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST.
IEICE Trans. Inf. Syst., 2008
A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals.
IEICE Trans. Electron., 2008
A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method.
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2006
TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure.
Proceedings of the 15th Asian Test Symposium, 2006
2005
IEICE Trans. Electron., 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
IEEE Signal Process. Lett., 2004
2002
Proceedings of the Advanced Internet Services and Applications, 2002
2001
A simple, scalable, and stable explicit rate allocation algorithm for MAX-MIN flow control with minimum rate guarantee.
IEEE/ACM Trans. Netw., 2001
Proceedings of the Global Telecommunications Conference, 2001
1999
Proceedings of the IEEE International Conference On Computer Design, 1999
1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
1996
Proceedings of the 28th conference on Winter simulation, 1996
1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
1983
Proceedings of the 20th Design Automation Conference, 1983
1981
Proceedings of the 18th Design Automation Conference, 1981